URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [bench/] [verilog/] [tb_openMSP430_fpga.v] - Diff between revs 37 and 94

Rev 37	Rev 94
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 37 $`	`// $Rev: 94 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $`	`// $LastChangedDate: 2011-02-24 21:33:35 +0100 (Thu, 24 Feb 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "timescale.v"	`include "timescale.v"
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module tb_openMSP430_fpga;`	`module tb_openMSP430_fpga;`
Line 121...	Line 121...
`//------------------------------`	`//------------------------------`

`initial`	`initial`
`begin`	`begin`
`// Read memory file`	`// Read memory file`
`$readmemh("./pmem.mem", pmem);`	`#10 $readmemh("./pmem.mem", pmem);`

`// Update Xilinx memory banks`	`// Update Xilinx memory banks`
`for (i=0; i<2048; i=i+1)`	`for (i=0; i<2048; i=i+1)`
`begin`	`begin`
`dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];`	`dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];`