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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [driver_7segment.v] - Diff between revs 28 and 104

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 23 $
// $Rev: 104 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
 
 
 
module  driver_7segment (
module  driver_7segment (
 
 
// OUTPUTs
// OUTPUTs
    per_dout,                       // Peripheral data output
    per_dout,                       // Peripheral data output

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