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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 104 $
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// $Rev: 109 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
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// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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module driver_7segment (
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module driver_7segment (
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// OUTPUTs
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// OUTPUTs
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// INPUTs
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// INPUTs
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mclk, // Main system clock
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mclk, // Main system clock
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per_addr, // Peripheral address
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per_addr, // Peripheral address
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per_din, // Peripheral data input
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per_din, // Peripheral data input
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per_en, // Peripheral enable (high active)
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per_en, // Peripheral enable (high active)
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per_wen, // Peripheral write enable (high active)
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per_we, // Peripheral write enable (high active)
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puc // Main system reset
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puc // Main system reset
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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//=========
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//=========
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [7:0] per_addr; // Peripheral address
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input [7:0] per_addr; // Peripheral address
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input [15:0] per_din; // Peripheral data input
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input [15:0] per_din; // Peripheral data input
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input per_en; // Peripheral enable (high active)
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input per_en; // Peripheral enable (high active)
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input [1:0] per_wen; // Peripheral write enable (high active)
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input [1:0] per_we; // Peripheral write enable (high active)
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input puc; // Main system reset
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input puc; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) PARAMETER DECLARATION
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// 1) PARAMETER DECLARATION
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(DIGIT3 /2): reg_dec = DIGIT3_D;
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(DIGIT3 /2): reg_dec = DIGIT3_D;
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default : reg_dec = {256{1'b0}};
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default : reg_dec = {256{1'b0}};
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endcase
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endcase
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// Read/Write probes
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// Read/Write probes
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wire reg_lo_write = per_wen[0] & per_en;
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wire reg_lo_write = per_we[0] & per_en;
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wire reg_hi_write = per_wen[1] & per_en;
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wire reg_hi_write = per_we[1] & per_en;
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wire reg_read = ~|per_wen & per_en;
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wire reg_read = ~|per_we & per_en;
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// Read/Write vectors
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// Read/Write vectors
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_hi_wr = reg_dec & {256{reg_hi_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_lo_wr = reg_dec & {256{reg_lo_write}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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wire [255:0] reg_rd = reg_dec & {256{reg_read}};
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