OpenCores

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//

//

// *Author(s):

// *Author(s):

//              - Olivier Girard,    olgirard@gmail.com

//              - Olivier Girard,    olgirard@gmail.com

//

//

//----------------------------------------------------------------------------

//----------------------------------------------------------------------------

// $Rev: 104 $

// $Rev: 109 $

// $LastChangedBy: olivier.girard $

// $LastChangedBy: olivier.girard $

// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $

// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $

//----------------------------------------------------------------------------

//----------------------------------------------------------------------------

`include "openMSP430_defines.v"

`include "openMSP430_defines.v"

module openMSP430_fpga (

module openMSP430_fpga (

Line 289...

//=============================================================================

//=============================================================================

// openMSP430 output buses

// openMSP430 output buses

wire         [7:0] per_addr;

wire         [7:0] per_addr;

wire        [15:0] per_din;

wire        [15:0] per_din;

wire         [1:0] per_wen;

wire         [1:0] per_we;

wire [`DMEM_MSB:0] dmem_addr;

wire [`DMEM_MSB:0] dmem_addr;

wire        [15:0] dmem_din;

wire        [15:0] dmem_din;

wire         [1:0] dmem_wen;

wire         [1:0] dmem_wen;

wire [`PMEM_MSB:0] pmem_addr;

wire [`PMEM_MSB:0] pmem_addr;

wire        [15:0] pmem_din;

wire        [15:0] pmem_din;

Line 487...

    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)

    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)

    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)

    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)

    .mclk         (mclk),         // Main system clock

    .mclk         (mclk),         // Main system clock

    .per_addr     (per_addr),     // Peripheral address

    .per_addr     (per_addr),     // Peripheral address

    .per_din      (per_din),      // Peripheral data input

    .per_din      (per_din),      // Peripheral data input

    .per_wen      (per_wen),      // Peripheral write enable (high active)

    .per_we       (per_we),       // Peripheral write enable (high active)

    .per_en       (per_en),       // Peripheral enable (high active)

    .per_en       (per_en),       // Peripheral enable (high active)

    .pmem_addr    (pmem_addr),    // Program Memory address

    .pmem_addr    (pmem_addr),    // Program Memory address

    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)

    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)

    .pmem_din     (pmem_din),     // Program Memory data input (optional)

    .pmem_din     (pmem_din),     // Program Memory data input (optional)

    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)

    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)

    .puc          (puc),          // Main system reset

    .puc          (puc),          // Main system reset

    .smclk_en     (smclk_en),     // SMCLK enable

    .smclk_en     (smclk_en),     // SMCLK enable

// INPUTs

// INPUTs

    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous)

    .dbg_en       (1'b1),         // Debug interface enable (asynchronous)

    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD

    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD

    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)

    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)

    .dmem_dout    (dmem_dout),    // Data Memory data output

    .dmem_dout    (dmem_dout),    // Data Memory data output

    .irq          (irq_bus),      // Maskable interrupts

    .irq          (irq_bus),      // Maskable interrupts

    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)

    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)

Line 558...

Line 560...

    .p5_din       (8'h00),         // Port 5 data input

    .p5_din       (8'h00),         // Port 5 data input

    .p6_din       (8'h00),         // Port 6 data input

    .p6_din       (8'h00),         // Port 6 data input

    .per_addr     (per_addr),      // Peripheral address

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .per_we       (per_we),        // Peripheral write enable (high active)

    .puc          (puc)            // Main system reset

    .puc          (puc)            // Main system reset

);

);

//

//

// Timer A

// Timer A

Line 588...

Line 590...

    .irq_ta0_acc  (irq_acc[9]),    // Interrupt request TACCR0 accepted

    .irq_ta0_acc  (irq_acc[9]),    // Interrupt request TACCR0 accepted

    .mclk         (mclk),          // Main system clock

    .mclk         (mclk),          // Main system clock

    .per_addr     (per_addr),      // Peripheral address

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .per_we       (per_we),        // Peripheral write enable (high active)

    .puc          (puc),           // Main system reset

    .puc          (puc),           // Main system reset

    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)

    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)

    .ta_cci0a     (ta_cci0a),      // Timer A capture 0 input A

    .ta_cci0a     (ta_cci0a),      // Timer A capture 0 input A

    .ta_cci0b     (ta_cci0b),      // Timer A capture 0 input B

    .ta_cci0b     (ta_cci0b),      // Timer A capture 0 input B

    .ta_cci1a     (ta_cci1a),      // Timer A capture 1 input A

    .ta_cci1a     (ta_cci1a),      // Timer A capture 1 input A

Line 627...

Line 629...

// INPUTs

// INPUTs

    .mclk         (mclk),          // Main system clock

    .mclk         (mclk),          // Main system clock

    .per_addr     (per_addr),      // Peripheral address

    .per_addr     (per_addr),      // Peripheral address

    .per_din      (per_din),       // Peripheral data input

    .per_din      (per_din),       // Peripheral data input

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_en       (per_en),        // Peripheral enable (high active)

    .per_wen      (per_wen),       // Peripheral write enable (high active)

    .per_we       (per_we),        // Peripheral write enable (high active)

    .puc          (puc)            // Main system reset

    .puc          (puc)            // Main system reset

);

);

//

//

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 104 and 109

Rev 104	Rev 109
Line 30...	Line 30...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 104 $`	`// $Rev: 109 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $`	`// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module openMSP430_fpga (`	`module openMSP430_fpga (`

Line 289...	Line 289...
`//=============================================================================`	`//=============================================================================`

`// openMSP430 output buses`	`// openMSP430 output buses`
`wire [7:0] per_addr;`	`wire [7:0] per_addr;`
`wire [15:0] per_din;`	`wire [15:0] per_din;`
`wire [1:0] per_wen;`	`wire [1:0] per_we;`
wire [`DMEM_MSB:0] dmem_addr;	wire [`DMEM_MSB:0] dmem_addr;
`wire [15:0] dmem_din;`	`wire [15:0] dmem_din;`
`wire [1:0] dmem_wen;`	`wire [1:0] dmem_wen;`
wire [`PMEM_MSB:0] pmem_addr;	wire [`PMEM_MSB:0] pmem_addr;
`wire [15:0] pmem_din;`	`wire [15:0] pmem_din;`
Line 487...	Line 487...
`.dmem_wen (dmem_wen), // Data Memory write enable (low active)`	`.dmem_wen (dmem_wen), // Data Memory write enable (low active)`
`.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)`	`.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)`
`.mclk (mclk), // Main system clock`	`.mclk (mclk), // Main system clock`
`.per_addr (per_addr), // Peripheral address`	`.per_addr (per_addr), // Peripheral address`
`.per_din (per_din), // Peripheral data input`	`.per_din (per_din), // Peripheral data input`
`.per_wen (per_wen), // Peripheral write enable (high active)`	`.per_we (per_we), // Peripheral write enable (high active)`
`.per_en (per_en), // Peripheral enable (high active)`	`.per_en (per_en), // Peripheral enable (high active)`
`.pmem_addr (pmem_addr), // Program Memory address`	`.pmem_addr (pmem_addr), // Program Memory address`
`.pmem_cen (pmem_cen), // Program Memory chip enable (low active)`	`.pmem_cen (pmem_cen), // Program Memory chip enable (low active)`
`.pmem_din (pmem_din), // Program Memory data input (optional)`	`.pmem_din (pmem_din), // Program Memory data input (optional)`
`.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)`	`.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)`
`.puc (puc), // Main system reset`	`.puc (puc), // Main system reset`
`.smclk_en (smclk_en), // SMCLK enable`	`.smclk_en (smclk_en), // SMCLK enable`

`// INPUTs`	`// INPUTs`
	`.cpu_en (1'b1), // Enable CPU code execution (asynchronous)`
	`.dbg_en (1'b1), // Debug interface enable (asynchronous)`
`.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD`	`.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD`
`.dco_clk (clk_sys), // Fast oscillator (fast clock)`	`.dco_clk (clk_sys), // Fast oscillator (fast clock)`
`.dmem_dout (dmem_dout), // Data Memory data output`	`.dmem_dout (dmem_dout), // Data Memory data output`
`.irq (irq_bus), // Maskable interrupts`	`.irq (irq_bus), // Maskable interrupts`
`.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)`	`.lfxt_clk (1'b0), // Low frequency oscillator (typ 32kHz)`
Line 558...	Line 560...
`.p5_din (8'h00), // Port 5 data input`	`.p5_din (8'h00), // Port 5 data input`
`.p6_din (8'h00), // Port 6 data input`	`.p6_din (8'h00), // Port 6 data input`
`.per_addr (per_addr), // Peripheral address`	`.per_addr (per_addr), // Peripheral address`
`.per_din (per_din), // Peripheral data input`	`.per_din (per_din), // Peripheral data input`
`.per_en (per_en), // Peripheral enable (high active)`	`.per_en (per_en), // Peripheral enable (high active)`
`.per_wen (per_wen), // Peripheral write enable (high active)`	`.per_we (per_we), // Peripheral write enable (high active)`
`.puc (puc) // Main system reset`	`.puc (puc) // Main system reset`
`);`	`);`

`//`	`//`
`// Timer A`	`// Timer A`
Line 588...	Line 590...
`.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted`	`.irq_ta0_acc (irq_acc[9]), // Interrupt request TACCR0 accepted`
`.mclk (mclk), // Main system clock`	`.mclk (mclk), // Main system clock`
`.per_addr (per_addr), // Peripheral address`	`.per_addr (per_addr), // Peripheral address`
`.per_din (per_din), // Peripheral data input`	`.per_din (per_din), // Peripheral data input`
`.per_en (per_en), // Peripheral enable (high active)`	`.per_en (per_en), // Peripheral enable (high active)`
`.per_wen (per_wen), // Peripheral write enable (high active)`	`.per_we (per_we), // Peripheral write enable (high active)`
`.puc (puc), // Main system reset`	`.puc (puc), // Main system reset`
`.smclk_en (smclk_en), // SMCLK enable (from CPU)`	`.smclk_en (smclk_en), // SMCLK enable (from CPU)`
`.ta_cci0a (ta_cci0a), // Timer A capture 0 input A`	`.ta_cci0a (ta_cci0a), // Timer A capture 0 input A`
`.ta_cci0b (ta_cci0b), // Timer A capture 0 input B`	`.ta_cci0b (ta_cci0b), // Timer A capture 0 input B`
`.ta_cci1a (ta_cci1a), // Timer A capture 1 input A`	`.ta_cci1a (ta_cci1a), // Timer A capture 1 input A`
Line 627...	Line 629...
`// INPUTs`	`// INPUTs`
`.mclk (mclk), // Main system clock`	`.mclk (mclk), // Main system clock`
`.per_addr (per_addr), // Peripheral address`	`.per_addr (per_addr), // Peripheral address`
`.per_din (per_din), // Peripheral data input`	`.per_din (per_din), // Peripheral data input`
`.per_en (per_en), // Peripheral enable (high active)`	`.per_en (per_en), // Peripheral enable (high active)`
`.per_wen (per_wen), // Peripheral write enable (high active)`	`.per_we (per_we), // Peripheral write enable (high active)`
`.puc (puc) // Main system reset`	`.puc (puc) // Main system reset`
`);`	`);`


`//`	`//`