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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 109 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module openMSP430_fpga (
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module openMSP430_fpga (
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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// openMSP430 output buses
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// openMSP430 output buses
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wire [7:0] per_addr;
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wire [13:0] per_addr;
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wire [15:0] per_din;
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wire [15:0] per_din;
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wire [1:0] per_we;
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wire [1:0] per_we;
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wire [`DMEM_MSB:0] dmem_addr;
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wire [`DMEM_MSB:0] dmem_addr;
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wire [15:0] dmem_din;
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wire [15:0] dmem_din;
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wire [1:0] dmem_wen;
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wire [1:0] dmem_wen;
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_addr (pmem_addr), // Program Memory address
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_din (pmem_din), // Program Memory data input (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
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.puc (puc), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable
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.smclk_en (smclk_en), // SMCLK enable
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// INPUTs
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// INPUTs
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.cpu_en (1'b1), // Enable CPU code execution (asynchronous)
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.cpu_en (1'b1), // Enable CPU code execution (asynchronous)
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.dbg_en (1'b1), // Debug interface enable (asynchronous)
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.dbg_en (1'b1), // Debug interface enable (asynchronous)
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Line 561... |
Line 561... |
.p6_din (8'h00), // Port 6 data input
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.p6_din (8'h00), // Port 6 data input
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc_rst (puc_rst) // Main system reset
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);
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);
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//
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//
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// Timer A
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// Timer A
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//----------------------------------------------
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//----------------------------------------------
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Line 591... |
.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.smclk_en (smclk_en), // SMCLK enable (from CPU)
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.ta_cci0a (ta_cci0a), // Timer A capture 0 input A
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.ta_cci0a (ta_cci0a), // Timer A capture 0 input A
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.ta_cci0b (ta_cci0b), // Timer A capture 0 input B
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.ta_cci0b (ta_cci0b), // Timer A capture 0 input B
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.ta_cci1a (ta_cci1a), // Timer A capture 1 input A
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.ta_cci1a (ta_cci1a), // Timer A capture 1 input A
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.ta_cci1b (1'b0), // Timer A capture 1 input B
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.ta_cci1b (1'b0), // Timer A capture 1 input B
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Line 630... |
Line 630... |
.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.per_addr (per_addr), // Peripheral address
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.per_addr (per_addr), // Peripheral address
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.per_din (per_din), // Peripheral data input
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.per_din (per_din), // Peripheral data input
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.per_en (per_en), // Peripheral enable (high active)
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.per_en (per_en), // Peripheral enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.per_we (per_we), // Peripheral write enable (high active)
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.puc (puc) // Main system reset
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.puc_rst (puc_rst) // Main system reset
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);
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);
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//
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//
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// Combine peripheral data buses
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// Combine peripheral data buses
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