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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 111 and 136

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Rev 111 Rev 136
Line 30... Line 30... 
//
 
//
 
// *Author(s):
 
// *Author(s):
 
//              - Olivier Girard,    olgirard@gmail.com
 
//              - Olivier Girard,    olgirard@gmail.com
 
//
 
//
 
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
 
// $Rev: 111 $
 
// $Rev: 136 $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
 
// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
 
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
 
`include "openMSP430_defines.v"
 
`include "openMSP430_defines.v"
 
 
 
 
 
module openMSP430_fpga (
 
module openMSP430_fpga (
 
 
 
 
Line 325... Line 325... 
wire        [15:0] per_dout_tA;
 
wire        [15:0] per_dout_tA;
 
 
 
 
 
// 7 segment driver
 
// 7 segment driver
 
wire        [15:0] per_dout_7seg;
 
wire        [15:0] per_dout_7seg;
 
 
 
 
 
 
 
// Simple UART
 
 
 
wire               irq_uart_rx;
 
 
 
wire               irq_uart_tx;
 
 
 
wire        [15:0] per_dout_uart;
 
 
 
wire               hw_uart_txd;
 
 
 
wire               hw_uart_rxd;
 
 
 
 
 
 
 
 
 
// Others
 
// Others
 
wire               reset_pin;
 
wire               reset_pin;
 
 
 
 
 
 
 
 
 
//=============================================================================
 
//=============================================================================
Line 476... Line 484... 
//=============================================================================
 
//=============================================================================
 
 
 
 
 
openMSP430 openMSP430_0 (
 
openMSP430 openMSP430_0 (
 
 
 
 
 
// OUTPUTs
 
// OUTPUTs
 
    .aclk_en      (aclk_en),      // ACLK enable
 
    .aclk         (),             // ASIC ONLY: ACLK
 
 
 
    .aclk_en      (aclk_en),      // FPGA ONLY: ACLK enable
 
    .dbg_freeze   (dbg_freeze),   // Freeze peripherals
 
    .dbg_freeze   (dbg_freeze),   // Freeze peripherals
 
    .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
 
    .dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
 
 
 
    .dco_enable   (),             // ASIC ONLY: Fast oscillator enable
 
 
 
    .dco_wkup     (),             // ASIC ONLY: Fast oscillator wake-up (asynchronous)
 
    .dmem_addr    (dmem_addr),    // Data Memory address
 
    .dmem_addr    (dmem_addr),    // Data Memory address
 
    .dmem_cen     (dmem_cen),     // Data Memory chip enable (low active)
 
    .dmem_cen     (dmem_cen),     // Data Memory chip enable (low active)
 
    .dmem_din     (dmem_din),     // Data Memory data input
 
    .dmem_din     (dmem_din),     // Data Memory data input
 
    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)
 
    .dmem_wen     (dmem_wen),     // Data Memory write enable (low active)
 
    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)
 
    .irq_acc      (irq_acc),      // Interrupt request accepted (one-hot signal)
 
 
 
    .lfxt_enable  (),             // ASIC ONLY: Low frequency oscillator enable
 
 
 
    .lfxt_wkup    (),             // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
 
    .mclk         (mclk),         // Main system clock
 
    .mclk         (mclk),         // Main system clock
 
    .per_addr     (per_addr),     // Peripheral address
 
    .per_addr     (per_addr),     // Peripheral address
 
    .per_din      (per_din),      // Peripheral data input
 
    .per_din      (per_din),      // Peripheral data input
 
    .per_we       (per_we),       // Peripheral write enable (high active)
 
    .per_we       (per_we),       // Peripheral write enable (high active)
 
    .per_en       (per_en),       // Peripheral enable (high active)
 
    .per_en       (per_en),       // Peripheral enable (high active)
 
    .pmem_addr    (pmem_addr),    // Program Memory address
 
    .pmem_addr    (pmem_addr),    // Program Memory address
 
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
 
    .pmem_cen     (pmem_cen),     // Program Memory chip enable (low active)
 
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
 
    .pmem_din     (pmem_din),     // Program Memory data input (optional)
 
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
 
    .pmem_wen     (pmem_wen),     // Program Memory write enable (low active) (optional)
 
    .puc_rst      (puc_rst),      // Main system reset
 
    .puc_rst      (puc_rst),      // Main system reset
 
    .smclk_en     (smclk_en),     // SMCLK enable
 
    .smclk        (),             // ASIC ONLY: SMCLK
 
 
 
    .smclk_en     (smclk_en),     // FPGA ONLY: SMCLK enable
 
 
 
 
 
// INPUTs
 
// INPUTs
 
    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous)
 
    .cpu_en       (1'b1),         // Enable CPU code execution (asynchronous and non-glitchy)
 
    .dbg_en       (1'b1),         // Debug interface enable (asynchronous)
 
    .dbg_en       (1'b1),         // Debug interface enable (asynchronous and non-glitchy)
 
    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
 
    .dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
 
    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)
 
    .dco_clk      (clk_sys),      // Fast oscillator (fast clock)
 
    .dmem_dout    (dmem_dout),    // Data Memory data output
 
    .dmem_dout    (dmem_dout),    // Data Memory data output
 
    .irq          (irq_bus),      // Maskable interrupts
 
    .irq          (irq_bus),      // Maskable interrupts
 
    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)
 
    .lfxt_clk     (1'b0),         // Low frequency oscillator (typ 32kHz)
 
    .nmi          (nmi),          // Non-maskable interrupt (asynchronous)
 
    .nmi          (nmi),          // Non-maskable interrupt (asynchronous)
 
    .per_dout     (per_dout),     // Peripheral data output
 
    .per_dout     (per_dout),     // Peripheral data output
 
    .pmem_dout    (pmem_dout),    // Program Memory data output
 
    .pmem_dout    (pmem_dout),    // Program Memory data output
 
    .reset_n      (reset_n)       // Reset Pin (low active)
 
    .reset_n      (reset_n),      // Reset Pin (low active, asynchronous and non-glitchy)
 
 
 
    .scan_enable  (1'b0),         // ASIC ONLY: Scan enable (active during scan shifting)
 
 
 
    .scan_mode    (1'b0),         // ASIC ONLY: Scan mode
 
 
 
    .wkup         (1'b0)          // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
 
);
 
);
 
 
 
 
 
 
 
 
 
//=============================================================================
 
//=============================================================================
 
// 5)  OPENMSP430 PERIPHERALS
 
// 5)  OPENMSP430 PERIPHERALS
Line 635... Line 652... 
    .puc_rst      (puc_rst)        // Main system reset
 
    .puc_rst      (puc_rst)        // Main system reset
 
);
 
);
 
 
 
 
 
 
 
 
 
//
 
//
 
 
 
// Simple full duplex UART (8N1 protocol)
 
 
 
//----------------------------------------
 
 
 
 
 
 
 
omsp_uart #(.BASE_ADDR(15'h0080)) uart_0 (
 
 
 
 
 
 
 
// OUTPUTs
 
 
 
    .irq_uart_rx  (irq_uart_rx),   // UART receive interrupt
 
 
 
    .irq_uart_tx  (irq_uart_tx),   // UART transmit interrupt
 
 
 
    .per_dout     (per_dout_uart), // Peripheral data output
 
 
 
    .uart_txd     (hw_uart_txd),   // UART Data Transmit (TXD)
 
 
 
 
 
 
 
// INPUTs
 
 
 
    .mclk         (mclk),          // Main system clock
 
 
 
    .per_addr     (per_addr),      // Peripheral address
 
 
 
    .per_din      (per_din),       // Peripheral data input
 
 
 
    .per_en       (per_en),        // Peripheral enable (high active)
 
 
 
    .per_we       (per_we),        // Peripheral write enable (high active)
 
 
 
    .puc_rst      (puc_rst),       // Main system reset
 
 
 
    .smclk_en     (smclk_en),      // SMCLK enable (from CPU)
 
 
 
    .uart_rxd     (hw_uart_rxd)    // UART Data Receive (RXD)
 
 
 
);
 
 
 
 
 
 
 
 
 
 
 
//
 
// Combine peripheral data buses
 
// Combine peripheral data buses
 
//-------------------------------
 
//-------------------------------
 
 
 
 
 
assign per_dout = per_dout_dio  |
 
assign per_dout = per_dout_dio  |
 
                  per_dout_tA   |
 
                  per_dout_tA   |
 
                  per_dout_7seg;
 
                  per_dout_7seg |
 
 
 
                  per_dout_uart;
 
 
 
 
 
//
 
//
 
// Assign interrupts
 
// Assign interrupts
 
//-------------------------------
 
//-------------------------------
 
 
 
 
Line 653... Line 695... 
                     1'b0,         // Vector 12  (0xFFF8)
 
                     1'b0,         // Vector 12  (0xFFF8)
 
                     1'b0,         // Vector 11  (0xFFF6)
 
                     1'b0,         // Vector 11  (0xFFF6)
 
                     1'b0,         // Vector 10  (0xFFF4) - Watchdog -
 
                     1'b0,         // Vector 10  (0xFFF4) - Watchdog -
 
                     irq_ta0,      // Vector  9  (0xFFF2)
 
                     irq_ta0,      // Vector  9  (0xFFF2)
 
                     irq_ta1,      // Vector  8  (0xFFF0)
 
                     irq_ta1,      // Vector  8  (0xFFF0)
 
                     1'b0,         // Vector  7  (0xFFEE)
 
                     irq_uart_rx,  // Vector  7  (0xFFEE)
 
                     1'b0,         // Vector  6  (0xFFEC)
 
                     irq_uart_tx,  // Vector  6  (0xFFEC)
 
                     1'b0,         // Vector  5  (0xFFEA)
 
                     1'b0,         // Vector  5  (0xFFEA)
 
                     1'b0,         // Vector  4  (0xFFE8)
 
                     1'b0,         // Vector  4  (0xFFE8)
 
                     irq_port2,    // Vector  3  (0xFFE6)
 
                     irq_port2,    // Vector  3  (0xFFE6)
 
                     irq_port1,    // Vector  2  (0xFFE4)
 
                     irq_port1,    // Vector  2  (0xFFE4)
 
                     1'b0,         // Vector  1  (0xFFE2)
 
                     1'b0,         // Vector  1  (0xFFE2)
Line 871... Line 913... 
// P1.1 (TX) and P2.2 (RX)
 
// P1.1 (TX) and P2.2 (RX)
 
assign p1_io_din      = 8'h00;
 
assign p1_io_din      = 8'h00;
 
assign p2_io_din[7:3] = 5'h00;
 
assign p2_io_din[7:3] = 5'h00;
 
assign p2_io_din[1:0] = 2'h0;
 
assign p2_io_din[1:0] = 2'h0;
 
 
 
 
 
// Mux the RS-232 port between IO port and the debug interface.
 
// Mux the RS-232 port between:
 
// The mux is controlled with the SW0 switch
 
//   - GPIO port P1.1 (TX) / P2.2 (RX)
 
wire   uart_txd_out = p3_din[0] ? dbg_uart_txd : p1_io_dout[1];
 
//   - the debug interface.
 
 
 
//   - the simple hardware UART
 
 
 
//
 
 
 
// The mux is controlled with the SW0/SW1 switches:
 
 
 
//        00 = debug interface
 
 
 
//        01 = GPIO
 
 
 
//        10 = simple hardware uart
 
 
 
//        11 = debug interface
 
 
 
wire sdi_select  = ({p3_din[1], p3_din[0]}==2'b00) |
 
 
 
                   ({p3_din[1], p3_din[0]}==2'b11);
 
 
 
wire gpio_select = ({p3_din[1], p3_din[0]}==2'b01);
 
 
 
wire uart_select = ({p3_din[1], p3_din[0]}==2'b10);
 
 
 
 
 
 
 
wire   uart_txd_out = gpio_select ? p1_io_dout[1]  :
 
 
 
                      uart_select ? hw_uart_txd    : dbg_uart_txd;
 
 
 
 
 
wire   uart_rxd_in;
 
wire   uart_rxd_in;
 
assign p2_io_din[2] = p3_din[0] ? 1'b1         : uart_rxd_in;
 
assign p2_io_din[2] = gpio_select ? uart_rxd_in : 1'b1;
 
assign dbg_uart_rxd = p3_din[0] ? uart_rxd_in  : 1'b1;
 
assign hw_uart_rxd  = uart_select ? uart_rxd_in : 1'b1;
 
 
 
assign dbg_uart_rxd = sdi_select  ? uart_rxd_in : 1'b1;
 
 
 
 
 
IBUF  UART_RXD_PIN   (.O(uart_rxd_in),                 .I(UART_RXD));
 
IBUF  UART_RXD_PIN   (.O(uart_rxd_in),                 .I(UART_RXD));
 
OBUF  UART_TXD_PIN   (.I(uart_txd_out),                .O(UART_TXD));
 
OBUF  UART_TXD_PIN   (.I(uart_txd_out),                .O(UART_TXD));
 
 
 
 
 
IBUF  UART_RXD_A_PIN (.O(),                            .I(UART_RXD_A));
 
IBUF  UART_RXD_A_PIN (.O(),                            .I(UART_RXD_A));

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