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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openMSP430_fpga.v] - Diff between revs 16 and 23

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 16 $
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:03:47 +0200 (Tue, 04 Aug 2009) $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`include "timescale.v"
 
`include "openMSP430_defines.v"
 
 
module openMSP430_fpga (
module openMSP430_fpga (
 
 
// Clock Sources
// Clock Sources
    CLK_50MHz,
    CLK_50MHz,

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