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Line 33... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $Rev: 85 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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|
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module omsp_clock_module (
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module omsp_clock_module (
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Line 156... |
//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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//============================================================================
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// Data output mux
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// Data output mux
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wire [15:0] bcsctl1_rd = (bcsctl1 & {8{reg_rd[BCSCTL1/2]}}) << (8 & {4{BCSCTL1[0]}});
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wire [15:0] bcsctl1_rd = {8'h00, (bcsctl1 & {8{reg_rd[BCSCTL1/2]}})} << (8 & {4{BCSCTL1[0]}});
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wire [15:0] bcsctl2_rd = (bcsctl2 & {8{reg_rd[BCSCTL2/2]}}) << (8 & {4{BCSCTL2[0]}});
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wire [15:0] bcsctl2_rd = {8'h00, (bcsctl2 & {8{reg_rd[BCSCTL2/2]}})} << (8 & {4{BCSCTL2[0]}});
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wire [15:0] per_dout = bcsctl1_rd |
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wire [15:0] per_dout = bcsctl1_rd |
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bcsctl2_rd;
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bcsctl2_rd;
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Line 188... |
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// Generate ACLK
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// Generate ACLK
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//----------------------------
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//----------------------------
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reg aclk_en;
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reg [2:0] aclk_div;
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reg [2:0] aclk_div;
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wire aclk_en = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
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wire aclk_en_nxt = lfxt_clk_en & ((bcsctl1[`DIVAx]==2'b00) ? 1'b1 :
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(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
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(bcsctl1[`DIVAx]==2'b01) ? aclk_div[0] :
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(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
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(bcsctl1[`DIVAx]==2'b10) ? &aclk_div[1:0] :
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&aclk_div[2:0]);
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&aclk_div[2:0]);
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) aclk_en <= 1'b0;
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else aclk_en <= aclk_en_nxt;
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always @ (posedge mclk or posedge puc)
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if (puc) aclk_div <= 3'h0;
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if (puc) aclk_div <= 3'h0;
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else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
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else if ((bcsctl1[`DIVAx]!=2'b00) & lfxt_clk_en) aclk_div <= aclk_div+3'h1;
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// Generate SMCLK
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// Generate SMCLK
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//----------------------------
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//----------------------------
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reg smclk_en;
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reg [2:0] smclk_div;
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reg [2:0] smclk_div;
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wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
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wire smclk_in = ~scg1 & (bcsctl2[`SELS] ? lfxt_clk_en : 1'b1);
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wire smclk_en = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
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wire smclk_en_nxt = smclk_in & ((bcsctl2[`DIVSx]==2'b00) ? 1'b1 :
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(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
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(bcsctl2[`DIVSx]==2'b01) ? smclk_div[0] :
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(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
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(bcsctl2[`DIVSx]==2'b10) ? &smclk_div[1:0] :
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&smclk_div[2:0]);
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&smclk_div[2:0]);
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always @ (posedge mclk or posedge puc)
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always @ (posedge mclk or posedge puc)
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if (puc) smclk_en <= 1'b0;
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else smclk_en <= smclk_en_nxt;
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always @ (posedge mclk or posedge puc)
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if (puc) smclk_div <= 3'h0;
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if (puc) smclk_div <= 3'h0;
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else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
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else if ((bcsctl2[`DIVSx]!=2'b00) & smclk_in) smclk_div <= smclk_div+3'h1;
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//=============================================================================
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//=============================================================================
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