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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg.v] - Diff between revs 155 and 176

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Rev 155 Rev 176
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 155 $
// $Rev: 176 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
// $LastChangedDate: 2013-01-30 22:22:50 +0100 (Wed, 30 Jan 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 77... Line 77...
    dbg_uart_rxd,                      // Debug interface: UART RXD (asynchronous)
    dbg_uart_rxd,                      // Debug interface: UART RXD (asynchronous)
    decode_noirq,                      // Frontend decode instruction
    decode_noirq,                      // Frontend decode instruction
    eu_mab,                            // Execution-Unit Memory address bus
    eu_mab,                            // Execution-Unit Memory address bus
    eu_mb_en,                          // Execution-Unit Memory bus enable
    eu_mb_en,                          // Execution-Unit Memory bus enable
    eu_mb_wr,                          // Execution-Unit Memory bus write transfer
    eu_mb_wr,                          // Execution-Unit Memory bus write transfer
    eu_mdb_in,                         // Memory data bus input
 
    eu_mdb_out,                        // Memory data bus output
 
    exec_done,                         // Execution completed
 
    fe_mb_en,                          // Frontend Memory bus enable
 
    fe_mdb_in,                         // Frontend Memory data bus input
    fe_mdb_in,                         // Frontend Memory data bus input
    pc,                                // Program counter
    pc,                                // Program counter
    puc_pnd_set                        // PUC pending set for the serial debug interface
    puc_pnd_set                        // PUC pending set for the serial debug interface
);
);
 
 
Line 120... Line 116...
input               dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
input               dbg_uart_rxd;      // Debug interface: UART RXD (asynchronous)
input               decode_noirq;      // Frontend decode instruction
input               decode_noirq;      // Frontend decode instruction
input        [15:0] eu_mab;            // Execution-Unit Memory address bus
input        [15:0] eu_mab;            // Execution-Unit Memory address bus
input               eu_mb_en;          // Execution-Unit Memory bus enable
input               eu_mb_en;          // Execution-Unit Memory bus enable
input         [1:0] eu_mb_wr;          // Execution-Unit Memory bus write transfer
input         [1:0] eu_mb_wr;          // Execution-Unit Memory bus write transfer
input        [15:0] eu_mdb_in;         // Memory data bus input
 
input        [15:0] eu_mdb_out;        // Memory data bus output
 
input               exec_done;         // Execution completed
 
input               fe_mb_en;          // Frontend Memory bus enable
 
input        [15:0] fe_mdb_in;         // Frontend Memory data bus input
input        [15:0] fe_mdb_in;         // Frontend Memory data bus input
input        [15:0] pc;                // Program counter
input        [15:0] pc;                // Program counter
input               puc_pnd_set;       // PUC pending set for the serial debug interface
input               puc_pnd_set;       // PUC pending set for the serial debug interface
 
 
 
 
Line 433... Line 425...
wire        mem_addr_wr  = reg_wr[MEM_ADDR];
wire        mem_addr_wr  = reg_wr[MEM_ADDR];
wire        dbg_mem_acc  = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire        dbg_mem_acc  = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire        dbg_reg_acc  = ( dbg_reg_wr | (dbg_rd_rdy &  mem_ctl[2]));
wire        dbg_reg_acc  = ( dbg_reg_wr | (dbg_rd_rdy &  mem_ctl[2]));
 
 
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000)         ? 16'h0000 :
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000)         ? 16'h0000 :
                           (dbg_mem_acc & ~mem_bw)     ? 16'h0002 :
                           (mem_burst &  dbg_mem_acc & ~mem_bw)      ? 16'h0002 :
                           (dbg_mem_acc | dbg_reg_acc) ? 16'h0001 : 16'h0000;
                           (mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
 
 
always @ (posedge dbg_clk or posedge dbg_rst)
always @ (posedge dbg_clk or posedge dbg_rst)
  if (dbg_rst)          mem_addr <=  16'h0000;
  if (dbg_rst)          mem_addr <=  16'h0000;
  else if (mem_addr_wr) mem_addr <=  dbg_din;
  else if (mem_addr_wr) mem_addr <=  dbg_din;
  else                  mem_addr <=  mem_addr + mem_addr_inc;
  else                  mem_addr <=  mem_addr + mem_addr_inc;
Line 485... Line 477...
    .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
    .brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_rst    (dbg_rst),     // Debug unit reset
    .dbg_rst    (dbg_rst),     // Debug unit reset
 
    .decode_noirq (decode_noirq), // Frontend decode instruction
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mdb_in  (eu_mdb_in),   // Memory data bus input
 
    .eu_mdb_out (eu_mdb_out),  // Memory data bus output
 
    .exec_done  (exec_done),   // Execution completed
 
    .fe_mb_en   (fe_mb_en),    // Frontend Memory bus enable
 
    .pc         (pc)           // Program counter
    .pc         (pc)           // Program counter
);
);
 
 
`else
`else
assign brk0_halt =  1'b0;
assign brk0_halt =  1'b0;
Line 527... Line 516...
    .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
    .brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_rst    (dbg_rst),     // Debug unit reset
    .dbg_rst    (dbg_rst),     // Debug unit reset
 
    .decode_noirq (decode_noirq), // Frontend decode instruction
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mdb_in  (eu_mdb_in),   // Memory data bus input
 
    .eu_mdb_out (eu_mdb_out),  // Memory data bus output
 
    .exec_done  (exec_done),   // Execution completed
 
    .fe_mb_en   (fe_mb_en),    // Frontend Memory bus enable
 
    .pc         (pc)           // Program counter
    .pc         (pc)           // Program counter
);
);
 
 
`else
`else
assign brk1_halt =  1'b0;
assign brk1_halt =  1'b0;
Line 569... Line 555...
    .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
    .brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_rst    (dbg_rst),     // Debug unit reset
    .dbg_rst    (dbg_rst),     // Debug unit reset
 
    .decode_noirq (decode_noirq), // Frontend decode instruction
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mdb_in  (eu_mdb_in),   // Memory data bus input
 
    .eu_mdb_out (eu_mdb_out),  // Memory data bus output
 
    .exec_done  (exec_done),   // Execution completed
 
    .fe_mb_en   (fe_mb_en),    // Frontend Memory bus enable
 
    .pc         (pc)           // Program counter
    .pc         (pc)           // Program counter
);
);
 
 
`else
`else
assign brk2_halt =  1'b0;
assign brk2_halt =  1'b0;
Line 611... Line 594...
    .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
    .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
    .brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_clk    (dbg_clk),     // Debug unit clock
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_din    (dbg_din),     // Debug register data input
    .dbg_rst    (dbg_rst),     // Debug unit reset
    .dbg_rst    (dbg_rst),     // Debug unit reset
 
    .decode_noirq (decode_noirq), // Frontend decode instruction
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mab     (eu_mab),      // Execution-Unit Memory address bus
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_en   (eu_mb_en),    // Execution-Unit Memory bus enable
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mb_wr   (eu_mb_wr),    // Execution-Unit Memory bus write transfer
    .eu_mdb_in  (eu_mdb_in),   // Memory data bus input
 
    .eu_mdb_out (eu_mdb_out),  // Memory data bus output
 
    .exec_done  (exec_done),   // Execution completed
 
    .fe_mb_en   (fe_mb_en),    // Frontend Memory bus enable
 
    .pc         (pc)           // Program counter
    .pc         (pc)           // Program counter
);
);
 
 
`else
`else
assign brk3_halt =  1'b0;
assign brk3_halt =  1'b0;

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