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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_dbg.v] - Diff between revs 84 and 85

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Rev 84 Rev 85
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 84 $
// $Rev: 85 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-01-23 21:00:36 +0100 (Sun, 23 Jan 2011) $
// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  omsp_dbg (
module  omsp_dbg (
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// Read/Write probes
// Read/Write probes
wire         reg_write =  dbg_wr;
wire         reg_write =  dbg_wr;
wire         reg_read  =  1'b1;
wire         reg_read  =  1'b1;
 
 
// Read/Write vectors
// Read/Write vectors
wire [511:0] reg_wr    = reg_dec & {64{reg_write}};
wire  [63:0] reg_wr    = reg_dec & {64{reg_write}};
wire [511:0] reg_rd    = reg_dec & {64{reg_read}};
wire  [63:0] reg_rd    = reg_dec & {64{reg_read}};
 
 
 
 
//=============================================================================
//=============================================================================
// 3)  REGISTER: CORE INTERFACE
// 3)  REGISTER: CORE INTERFACE
//=============================================================================
//=============================================================================

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