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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $Rev: 74 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module omsp_dbg_uart (
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module omsp_dbg_uart (
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assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
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assign sync_done = (uart_state==RX_SYNC) & rxd_re & sync_busy;
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`ifdef DBG_UART_AUTO_SYNC
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`ifdef DBG_UART_AUTO_SYNC
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reg [14:0] sync_cnt;
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reg [`DBG_UART_XFER_CNT_W+2:0] sync_cnt;
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) sync_cnt <= 15'h7ff8;
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if (por) sync_cnt <= {{`DBG_UART_XFER_CNT_W{1'b1}}, 3'b000};
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else if (sync_busy) sync_cnt <= sync_cnt+15'h0001;
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else if (sync_busy) sync_cnt <= sync_cnt+{{`DBG_UART_XFER_CNT_W+2{1'b0}}, 1'b1};
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wire [11:0] bit_cnt_max = sync_cnt[14:3];
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = sync_cnt[`DBG_UART_XFER_CNT_W+2:3];
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`else
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`else
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wire [11:0] bit_cnt_max = `DBG_UART_CNT;
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wire [`DBG_UART_XFER_CNT_W-1:0] bit_cnt_max = `DBG_UART_CNT;
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`endif
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`endif
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//=============================================================================
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//=============================================================================
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// 4) UART RECEIVE / TRANSMIT
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// 4) UART RECEIVE / TRANSMIT
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//=============================================================================
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//=============================================================================
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// Transfer counter
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// Transfer counter
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//------------------------
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//------------------------
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reg [3:0] xfer_bit;
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reg [3:0] xfer_bit;
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reg [11:0] xfer_cnt;
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reg [`DBG_UART_XFER_CNT_W-1:0] xfer_cnt;
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire txd_start = dbg_rd_rdy | (xfer_done & (uart_state==TX_DATA1));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire rxd_start = (xfer_bit==4'h0) & rxd_fe & ((uart_state!=RX_SYNC));
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt==12'h000);
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wire xfer_bit_inc = (xfer_bit!=4'h0) & (xfer_cnt=={`DBG_UART_XFER_CNT_W{1'b0}});
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assign xfer_done = (xfer_bit==4'hb);
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assign xfer_done = (xfer_bit==4'hb);
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) xfer_bit <= 4'h0;
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if (por) xfer_bit <= 4'h0;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (txd_start | rxd_start) xfer_bit <= 4'h1;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_done) xfer_bit <= 4'h0;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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else if (xfer_bit_inc) xfer_bit <= xfer_bit+4'h1;
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always @ (posedge mclk or posedge por)
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always @ (posedge mclk or posedge por)
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if (por) xfer_cnt <= 12'h000;
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if (por) xfer_cnt <= {`DBG_UART_XFER_CNT_W{1'b0}};
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else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[11:1]};
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else if (rxd_start) xfer_cnt <= {1'b0, bit_cnt_max[`DBG_UART_XFER_CNT_W-1:1]};
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else if (txd_start | xfer_bit_inc) xfer_cnt <= bit_cnt_max;
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else xfer_cnt <= xfer_cnt+12'hfff;
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else xfer_cnt <= xfer_cnt+{`DBG_UART_XFER_CNT_W{1'b1}};
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// Receive/Transmit buffer
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// Receive/Transmit buffer
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//-------------------------
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//-------------------------
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wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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wire [19:0] xfer_buf_nxt = {rxd_s, xfer_buf[19:1]};
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