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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 105 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 76... |
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inst_type, // Decoded Instruction type
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inst_type, // Decoded Instruction type
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mclk, // Main system clock
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mclk, // Main system clock
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mdb_in, // Memory data bus input
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mdb_in, // Memory data bus input
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pc, // Program counter
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pc, // Program counter
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pc_nxt, // Next PC value (for CALL & IRQ)
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pc_nxt, // Next PC value (for CALL & IRQ)
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puc // Main system reset
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puc_rst // Main system reset
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);
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);
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|
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output cpuoff; // Turns off the CPU
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output cpuoff; // Turns off the CPU
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Line 117... |
input [2:0] inst_type; // Decoded Instruction type
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input [2:0] inst_type; // Decoded Instruction type
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] mdb_in; // Memory data bus input
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input [15:0] mdb_in; // Memory data bus input
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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input [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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input puc; // Main system reset
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input puc_rst; // Main system reset
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//=============================================================================
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//=============================================================================
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
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//=============================================================================
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//=============================================================================
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_bw (inst_bw), // Decoded Inst: byte width
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.inst_dest (inst_dest), // Register destination selection
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.inst_dest (inst_dest), // Register destination selection
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.inst_src (inst_src), // Register source selection
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.inst_src (inst_src), // Register source selection
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.mclk (mclk), // Main system clock
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.mclk (mclk), // Main system clock
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.pc (pc), // Program counter
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.pc (pc), // Program counter
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.puc (puc), // Main system reset
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.puc_rst (puc_rst), // Main system reset
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.reg_dest_val (alu_out), // Selected register destination value
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.reg_dest_val (alu_out), // Selected register destination value
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.reg_dest_wr (reg_dest_wr), // Write selected register destination
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.reg_dest_wr (reg_dest_wr), // Write selected register destination
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.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
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.reg_pc_call (reg_pc_call), // Trigger PC update for a CALL instruction
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.reg_sp_val (alu_out_add), // Stack Pointer next value
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.reg_sp_val (alu_out_add), // Stack Pointer next value
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.reg_sp_wr (reg_sp_wr), // Stack Pointer write
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.reg_sp_wr (reg_sp_wr), // Stack Pointer write
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Line 335... |
// Memory address bus
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// Memory address bus
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assign mab = alu_out_add[15:0];
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assign mab = alu_out_add[15:0];
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// Memory data bus output
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// Memory data bus output
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reg [15:0] mdb_out_nxt;
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reg [15:0] mdb_out_nxt;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) mdb_out_nxt <= 16'h0000;
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if (puc_rst) mdb_out_nxt <= 16'h0000;
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else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
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else if (e_state==`E_DST_RD) mdb_out_nxt <= pc_nxt;
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else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
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else if ((e_state==`E_EXEC & ~inst_so[`CALL]) |
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
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(e_state==`E_IRQ_0) | (e_state==`E_IRQ_2)) mdb_out_nxt <= alu_out;
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assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
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assign mdb_out = inst_bw ? {2{mdb_out_nxt[7:0]}} : mdb_out_nxt;
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// Format memory data bus input depending on BW
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// Format memory data bus input depending on BW
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reg mab_lsb;
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reg mab_lsb;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) mab_lsb <= 1'b0;
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if (puc_rst) mab_lsb <= 1'b0;
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else if (mb_en) mab_lsb <= alu_out_add[0];
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else if (mb_en) mab_lsb <= alu_out_add[0];
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assign mdb_in_bw = ~inst_bw ? mdb_in :
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assign mdb_in_bw = ~inst_bw ? mdb_in :
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mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
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mab_lsb ? {2{mdb_in[15:8]}} : mdb_in;
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// Memory data bus input buffer (buffer after a source read)
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// Memory data bus input buffer (buffer after a source read)
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reg mdb_in_buf_en;
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reg mdb_in_buf_en;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) mdb_in_buf_en <= 1'b0;
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if (puc_rst) mdb_in_buf_en <= 1'b0;
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else mdb_in_buf_en <= (e_state==`E_SRC_RD);
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else mdb_in_buf_en <= (e_state==`E_SRC_RD);
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|
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reg mdb_in_buf_valid;
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reg mdb_in_buf_valid;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) mdb_in_buf_valid <= 1'b0;
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if (puc_rst) mdb_in_buf_valid <= 1'b0;
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else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
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else if (e_state==`E_EXEC) mdb_in_buf_valid <= 1'b0;
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else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
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else if (mdb_in_buf_en) mdb_in_buf_valid <= 1'b1;
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reg [15:0] mdb_in_buf;
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reg [15:0] mdb_in_buf;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) mdb_in_buf <= 16'h0000;
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if (puc_rst) mdb_in_buf <= 16'h0000;
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else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
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else if (mdb_in_buf_en) mdb_in_buf <= mdb_in_bw;
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assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
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assign mdb_in_val = mdb_in_buf_valid ? mdb_in_buf : mdb_in_bw;
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