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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_execution_unit.v] - Diff between revs 136 and 176

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Rev 136 Rev 176
Line 34... Line 34...
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 136 $
// $Rev: 176 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
// $LastChangedDate: 2013-01-30 22:22:50 +0100 (Wed, 30 Jan 2013) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`else
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
`endif
`endif
Line 322... Line 322...
//=============================================================================
//=============================================================================
// 6)  MEMORY INTERFACE
// 6)  MEMORY INTERFACE
//=============================================================================
//=============================================================================
 
 
// Detect memory read/write access
// Detect memory read/write access
assign      mb_en     = ((e_state==`E_IRQ_1)  & ~inst_irq_rst)        |
wire        mb_rd_det = ((e_state==`E_SRC_RD) & ~inst_as[`IMM])       |
                        ((e_state==`E_IRQ_3)  & ~inst_irq_rst)        |
 
                        ((e_state==`E_SRC_RD) & ~inst_as[`IMM])       |
 
                         (e_state==`E_SRC_WR)                         |
 
                        ((e_state==`E_EXEC)   &  inst_so[`RETI])      |
                        ((e_state==`E_EXEC)   &  inst_so[`RETI])      |
                        ((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
                        ((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
                                              & ~inst_mov)            |
                                              & ~inst_mov);
                         (e_state==`E_DST_WR);
 
 
wire        mb_wr_det = ((e_state==`E_IRQ_1)  & ~inst_irq_rst)        |
 
                        ((e_state==`E_IRQ_3)  & ~inst_irq_rst)        |
 
                        ((e_state==`E_DST_WR) & ~inst_so[`RETI])      |
 
                         (e_state==`E_SRC_WR);
 
 
wire  [1:0] mb_wr_msk =  inst_alu[`EXEC_NO_WR]  ? 2'b00 :
wire  [1:0] mb_wr_msk =  inst_alu[`EXEC_NO_WR]  ? 2'b00 :
                        ~inst_bw                ? 2'b11 :
                        ~inst_bw                ? 2'b11 :
                         alu_out_add[0]         ? 2'b10 : 2'b01;
                         alu_out_add[0]         ? 2'b10 : 2'b01;
assign      mb_wr     = ({2{(e_state==`E_IRQ_1)}}  |
 
                         {2{(e_state==`E_IRQ_3)}}  |
assign      mb_en     = mb_rd_det | mb_wr_det;
                         {2{(e_state==`E_DST_WR)}} |
 
                         {2{(e_state==`E_SRC_WR)}}) & mb_wr_msk;
assign      mb_wr     = ({2{mb_wr_det}}) & mb_wr_msk;
 
 
 
 
 
 
// Memory address bus
// Memory address bus
assign      mab       = alu_out_add[15:0];
assign      mab       = alu_out_add[15:0];
 
 
// Memory data bus output
// Memory data bus output

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