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Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 136 $
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// $Rev: 176 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
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// $LastChangedDate: 2013-01-30 22:22:50 +0100 (Wed, 30 Jan 2013) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 322... |
Line 322... |
//=============================================================================
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//=============================================================================
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// 6) MEMORY INTERFACE
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// 6) MEMORY INTERFACE
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//=============================================================================
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//=============================================================================
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|
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// Detect memory read/write access
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// Detect memory read/write access
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assign mb_en = ((e_state==`E_IRQ_1) & ~inst_irq_rst) |
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wire mb_rd_det = ((e_state==`E_SRC_RD) & ~inst_as[`IMM]) |
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((e_state==`E_IRQ_3) & ~inst_irq_rst) |
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((e_state==`E_SRC_RD) & ~inst_as[`IMM]) |
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(e_state==`E_SRC_WR) |
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((e_state==`E_EXEC) & inst_so[`RETI]) |
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((e_state==`E_EXEC) & inst_so[`RETI]) |
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((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
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((e_state==`E_DST_RD) & ~inst_type[`INST_SO]
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& ~inst_mov) |
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& ~inst_mov);
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(e_state==`E_DST_WR);
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wire mb_wr_det = ((e_state==`E_IRQ_1) & ~inst_irq_rst) |
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((e_state==`E_IRQ_3) & ~inst_irq_rst) |
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((e_state==`E_DST_WR) & ~inst_so[`RETI]) |
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(e_state==`E_SRC_WR);
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wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :
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wire [1:0] mb_wr_msk = inst_alu[`EXEC_NO_WR] ? 2'b00 :
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~inst_bw ? 2'b11 :
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~inst_bw ? 2'b11 :
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alu_out_add[0] ? 2'b10 : 2'b01;
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alu_out_add[0] ? 2'b10 : 2'b01;
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assign mb_wr = ({2{(e_state==`E_IRQ_1)}} |
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{2{(e_state==`E_IRQ_3)}} |
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assign mb_en = mb_rd_det | mb_wr_det;
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{2{(e_state==`E_DST_WR)}} |
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{2{(e_state==`E_SRC_WR)}}) & mb_wr_msk;
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assign mb_wr = ({2{mb_wr_det}}) & mb_wr_msk;
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// Memory address bus
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// Memory address bus
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assign mab = alu_out_add[15:0];
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assign mab = alu_out_add[15:0];
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// Memory data bus output
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// Memory data bus output
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