| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 104 $
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// $Rev: 105 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
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// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 53... |
Line 53... |
inst_bw, // Decoded Inst: byte width
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inst_bw, // Decoded Inst: byte width
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inst_dest, // Decoded Inst: destination (one hot)
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inst_dest, // Decoded Inst: destination (one hot)
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inst_dext, // Decoded Inst: destination extended instruction word
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inst_dext, // Decoded Inst: destination extended instruction word
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inst_irq_rst, // Decoded Inst: Reset interrupt
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inst_irq_rst, // Decoded Inst: Reset interrupt
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inst_jmp, // Decoded Inst: Conditional jump
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inst_jmp, // Decoded Inst: Conditional jump
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inst_mov, // Decoded Inst: mov instruction
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inst_sext, // Decoded Inst: source extended instruction word
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inst_sext, // Decoded Inst: source extended instruction word
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inst_so, // Decoded Inst: Single-operand arithmetic
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inst_so, // Decoded Inst: Single-operand arithmetic
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inst_src, // Decoded Inst: source (one hot)
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inst_src, // Decoded Inst: source (one hot)
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inst_type, // Decoded Instruction type
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inst_type, // Decoded Instruction type
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irq_acc, // Interrupt request accepted (one-hot signal)
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irq_acc, // Interrupt request accepted (one-hot signal)
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| Line 94... |
Line 95... |
output inst_bw; // Decoded Inst: byte width
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output inst_bw; // Decoded Inst: byte width
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output [15:0] inst_dest; // Decoded Inst: destination (one hot)
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output [15:0] inst_dest; // Decoded Inst: destination (one hot)
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output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
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output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
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output inst_irq_rst; // Decoded Inst: Reset interrupt
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output inst_irq_rst; // Decoded Inst: Reset interrupt
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output [7:0] inst_jmp; // Decoded Inst: Conditional jump
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output [7:0] inst_jmp; // Decoded Inst: Conditional jump
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output inst_mov; // Decoded Inst: mov instruction
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output [15:0] inst_sext; // Decoded Inst: source extended instruction word
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output [15:0] inst_sext; // Decoded Inst: source extended instruction word
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output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
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output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
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output [15:0] inst_src; // Decoded Inst: source (one hot)
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output [15:0] inst_src; // Decoded Inst: source (one hot)
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output [2:0] inst_type; // Decoded Instruction type
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output [2:0] inst_type; // Decoded Instruction type
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
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| Line 419... |
Line 421... |
// 12'b100000000000: AND
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// 12'b100000000000: AND
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|
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wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [15:0] inst_to_1hot = one_hot16(ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
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|
|
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reg inst_mov;
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always @(posedge mclk or posedge puc)
|
|
if (puc) inst_mov <= 1'b0;
|
|
else if (decode) inst_mov <= inst_to_nxt[`MOV];
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//
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//
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// 4.5) SOURCE AND DESTINATION REGISTERS
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// 4.5) SOURCE AND DESTINATION REGISTERS
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//---------------------------------------
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//---------------------------------------
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|
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