| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 105 $
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// $Rev: 109 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-10 22:10:30 +0100 (Thu, 10 Mar 2011) $
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// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 66... |
Line 66... |
nmi_acc, // Non-Maskable interrupt request accepted
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nmi_acc, // Non-Maskable interrupt request accepted
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pc, // Program counter
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pc, // Program counter
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pc_nxt, // Next PC value (for CALL & IRQ)
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pc_nxt, // Next PC value (for CALL & IRQ)
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// INPUTs
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// INPUTs
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cpu_en_s, // Enable CPU code execution (synchronous)
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cpuoff, // Turns off the CPU
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cpuoff, // Turns off the CPU
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dbg_halt_cmd, // Halt CPU command
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dbg_halt_cmd, // Halt CPU command
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dbg_reg_sel, // Debug selected register for rd/wr access
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dbg_reg_sel, // Debug selected register for rd/wr access
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fe_pmem_wait, // Frontend wait for Instruction fetch
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fe_pmem_wait, // Frontend wait for Instruction fetch
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gie, // General interrupt enable
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gie, // General interrupt enable
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| Line 109... |
Line 110... |
output [15:0] pc; // Program counter
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output [15:0] pc; // Program counter
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output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
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// INPUTs
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// INPUTs
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//=========
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//=========
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input cpu_en_s; // Enable CPU code execution (synchronous)
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input cpuoff; // Turns off the CPU
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input cpuoff; // Turns off the CPU
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input dbg_halt_cmd; // Halt CPU command
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input dbg_halt_cmd; // Halt CPU command
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input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
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input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
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input fe_pmem_wait; // Frontend wait for Instruction fetch
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input fe_pmem_wait; // Frontend wait for Instruction fetch
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input gie; // General interrupt enable
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input gie; // General interrupt enable
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| Line 171... |
Line 173... |
parameter I_DEC = 3'h2; // New instruction ready for decode
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parameter I_DEC = 3'h2; // New instruction ready for decode
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parameter I_EXT1 = 3'h3; // 1st Extension word
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parameter I_EXT1 = 3'h3; // 1st Extension word
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parameter I_EXT2 = 3'h4; // 2nd Extension word
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parameter I_EXT2 = 3'h4; // 2nd Extension word
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parameter I_IDLE = 3'h5; // CPU is in IDLE mode
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parameter I_IDLE = 3'h5; // CPU is in IDLE mode
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// CPU on/off through the debug interface or cpu_en port
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wire cpu_halt_cmd = dbg_halt_cmd | ~cpu_en_s;
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// States Transitions
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// States Transitions
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always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
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always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
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exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
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exec_done or irq_detect or cpuoff or cpu_halt_cmd or e_state)
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case(i_state)
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case(i_state)
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I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
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I_IDLE : i_state_nxt = (irq_detect & ~cpu_halt_cmd) ? I_IRQ_FETCH :
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(~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
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(~cpuoff & ~cpu_halt_cmd) ? I_DEC : I_IDLE;
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I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
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I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
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I_IRQ_DONE : i_state_nxt = I_DEC;
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I_IRQ_DONE : i_state_nxt = I_DEC;
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I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
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I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
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(cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
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(cpuoff | cpu_halt_cmd) & exec_done ? I_IDLE :
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dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
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cpu_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
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pc_sw_wr ? I_DEC :
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pc_sw_wr ? I_DEC :
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~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
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~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
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(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
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(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
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I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
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I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
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pc_sw_wr ? I_DEC :
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pc_sw_wr ? I_DEC :
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| Line 206... |
Line 211... |
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// Debug interface cpu status
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// Debug interface cpu status
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reg dbg_halt_st;
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reg dbg_halt_st;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) dbg_halt_st <= 1'b0;
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if (puc) dbg_halt_st <= 1'b0;
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else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
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else dbg_halt_st <= cpu_halt_cmd & (i_state_nxt==I_IDLE);
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//=============================================================================
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//=============================================================================
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// 2) INTERRUPT HANDLING
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// 2) INTERRUPT HANDLING
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//=============================================================================
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//=============================================================================
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| Line 228... |
Line 233... |
always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_irq_rst <= 1'b1;
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if (puc) inst_irq_rst <= 1'b1;
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else if (exec_done) inst_irq_rst <= 1'b0;
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else if (exec_done) inst_irq_rst <= 1'b0;
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// Detect other interrupts
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// Detect other interrupts
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assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
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assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~cpu_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
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// Select interrupt vector
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// Select interrupt vector
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reg [3:0] irq_num;
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reg [3:0] irq_num;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) irq_num <= 4'hf;
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if (puc) irq_num <= 4'hf;
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| Line 287... |
Line 292... |
if (puc) pmem_busy <= 1'b0;
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if (puc) pmem_busy <= 1'b0;
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else pmem_busy <= fe_pmem_wait;
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else pmem_busy <= fe_pmem_wait;
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// Memory interface
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// Memory interface
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wire [15:0] mab = pc_nxt;
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wire [15:0] mab = pc_nxt;
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wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
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wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~cpu_halt_cmd);
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//
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//
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// 3.2) INSTRUCTION REGISTER
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// 3.2) INSTRUCTION REGISTER
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//--------------------------------
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//--------------------------------
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| Line 564... |
Line 569... |
1'b1 : inst_ad_nxt = 8'b01000000;
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1'b1 : inst_ad_nxt = 8'b01000000;
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default: inst_ad_nxt = 8'b00000001;
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default: inst_ad_nxt = 8'b00000001;
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endcase
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endcase
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else if (dest_reg==4'h0) // Addressing mode using R0
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else if (dest_reg==4'h0) // Addressing mode using R0
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case (ir[7])
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case (ir[7])
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2'b1 : inst_ad_nxt = 8'b00010000;
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1'b1 : inst_ad_nxt = 8'b00010000;
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default: inst_ad_nxt = 8'b00000001;
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default: inst_ad_nxt = 8'b00000001;
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endcase
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endcase
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else // General Addressing mode
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else // General Addressing mode
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case (ir[7])
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case (ir[7])
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2'b1 : inst_ad_nxt = 8'b00000010;
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1'b1 : inst_ad_nxt = 8'b00000010;
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default: inst_ad_nxt = 8'b00000001;
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default: inst_ad_nxt = 8'b00000001;
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endcase
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endcase
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end
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end
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reg [7:0] inst_ad;
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reg [7:0] inst_ad;
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| Line 588... |
Line 593... |
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// Operation size
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// Operation size
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reg inst_bw;
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reg inst_bw;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) inst_bw <= 1'b0;
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if (puc) inst_bw <= 1'b0;
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else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
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else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~cpu_halt_cmd;
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// Extended instruction size
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// Extended instruction size
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assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
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assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
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{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
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{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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| Line 643... |
Line 648... |
if (puc) exec_dext_rdy <= 1'b0;
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if (puc) exec_dext_rdy <= 1'b0;
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else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0;
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else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0;
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else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
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else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
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// Execution first state
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// Execution first state
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//wire [3:0] e_first_state = dbg_halt_cmd ? `E_IDLE :
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wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
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wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
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dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
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cpu_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
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cpuoff ? `E_IDLE :
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cpuoff ? `E_IDLE :
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src_acalc_pre ? `E_SRC_AD :
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src_acalc_pre ? `E_SRC_AD :
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src_rd_pre ? `E_SRC_RD :
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src_rd_pre ? `E_SRC_RD :
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dst_acalc_pre ? `E_DST_AD :
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dst_acalc_pre ? `E_DST_AD :
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dst_rd_pre ? `E_DST_RD : `E_EXEC;
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dst_rd_pre ? `E_DST_RD : `E_EXEC;
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