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Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $Rev: 54 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2010-01-27 19:25:43 +0100 (Wed, 27 Jan 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module omsp_frontend (
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module omsp_frontend (
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// OUTPUTs
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// OUTPUTs
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dbg_halt_st, // Halt/Run status from CPU
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dbg_halt_st, // Halt/Run status from CPU
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decode, // Frontend decode instruction
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decode_noirq, // Frontend decode instruction
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e_state, // Execution state
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e_state, // Execution state
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exec_done, // Execution completed
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exec_done, // Execution completed
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inst_ad, // Decoded Inst: destination addressing mode
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inst_ad, // Decoded Inst: destination addressing mode
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inst_as, // Decoded Inst: source addressing mode
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inst_as, // Decoded Inst: source addressing mode
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inst_alu, // ALU control signals
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inst_alu, // ALU control signals
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);
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);
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// OUTPUTs
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// OUTPUTs
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//=========
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//=========
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output dbg_halt_st; // Halt/Run status from CPU
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output dbg_halt_st; // Halt/Run status from CPU
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output decode; // Frontend decode instruction
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output decode_noirq; // Frontend decode instruction
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output [3:0] e_state; // Execution state
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output [3:0] e_state; // Execution state
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output exec_done; // Execution completed
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output exec_done; // Execution completed
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output [7:0] inst_ad; // Decoded Inst: destination addressing mode
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output [7:0] inst_ad; // Decoded Inst: destination addressing mode
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output [7:0] inst_as; // Decoded Inst: source addressing mode
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output [7:0] inst_as; // Decoded Inst: source addressing mode
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output [11:0] inst_alu; // ALU control signals
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output [11:0] inst_alu; // ALU control signals
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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if (puc) i_state <= I_IRQ_FETCH;
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if (puc) i_state <= I_IRQ_FETCH;
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else i_state <= i_state_nxt;
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else i_state <= i_state_nxt;
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// Utility signals
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// Utility signals
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wire decode = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE))) | irq_detect;
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wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE)));
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wire decode = decode_noirq | irq_detect;
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wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
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wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
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// Debug interface cpu status
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// Debug interface cpu status
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reg dbg_halt_st;
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reg dbg_halt_st;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc)
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