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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_frontend.v] - Diff between revs 85 and 91

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Rev 85 Rev 91
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 85 $
// $Rev: 91 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $
// $LastChangedDate: 2011-02-20 20:45:04 +0100 (Sun, 20 Feb 2011) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
`include "timescale.v"
`include "timescale.v"
`include "openMSP430_defines.v"
`include "openMSP430_defines.v"
 
 
module  omsp_frontend (
module  omsp_frontend (
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always @(posedge mclk or posedge puc)
always @(posedge mclk or posedge puc)
  if (puc)                      inst_irq_rst <= 1'b1;
  if (puc)                      inst_irq_rst <= 1'b1;
  else if (exec_done)           inst_irq_rst <= 1'b0;
  else if (exec_done)           inst_irq_rst <= 1'b0;
 
 
//  Detect other interrupts
//  Detect other interrupts
assign  irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE));
assign  irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & ~dbg_halt_st & (exec_done | (i_state==I_IDLE));
 
 
// Select interrupt vector
// Select interrupt vector
reg  [3:0] irq_num;
reg  [3:0] irq_num;
always @(posedge mclk or posedge puc)
always @(posedge mclk or posedge puc)
  if (puc)             irq_num <= 4'hf;
  if (puc)             irq_num <= 4'hf;

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