| Line 29... |
Line 29... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 109 $
|
// $Rev: 111 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
|
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 74... |
Line 74... |
fe_mab, // Frontend Memory address bus
|
fe_mab, // Frontend Memory address bus
|
fe_mb_en, // Frontend Memory bus enable
|
fe_mb_en, // Frontend Memory bus enable
|
mclk, // Main system clock
|
mclk, // Main system clock
|
per_dout, // Peripheral data output
|
per_dout, // Peripheral data output
|
pmem_dout, // Program Memory data output
|
pmem_dout, // Program Memory data output
|
puc // Main system reset
|
puc_rst // Main system reset
|
);
|
);
|
|
|
// OUTPUTs
|
// OUTPUTs
|
//=========
|
//=========
|
output [15:0] dbg_mem_din; // Debug unit Memory data input
|
output [15:0] dbg_mem_din; // Debug unit Memory data input
|
| Line 87... |
Line 87... |
output [15:0] dmem_din; // Data Memory data input
|
output [15:0] dmem_din; // Data Memory data input
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [1:0] dmem_wen; // Data Memory write enable (low active)
|
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
|
output [15:0] eu_mdb_in; // Execution Unit Memory data bus input
|
output [15:0] fe_mdb_in; // Frontend Memory data bus input
|
output [15:0] fe_mdb_in; // Frontend Memory data bus input
|
output fe_pmem_wait; // Frontend wait for Instruction fetch
|
output fe_pmem_wait; // Frontend wait for Instruction fetch
|
output [7:0] per_addr; // Peripheral address
|
output [13:0] per_addr; // Peripheral address
|
output [15:0] per_din; // Peripheral data input
|
output [15:0] per_din; // Peripheral data input
|
output [1:0] per_we; // Peripheral write enable (high active)
|
output [1:0] per_we; // Peripheral write enable (high active)
|
output per_en; // Peripheral enable (high active)
|
output per_en; // Peripheral enable (high active)
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
|
output pmem_cen; // Program Memory chip enable (low active)
|
output pmem_cen; // Program Memory chip enable (low active)
|
| Line 113... |
Line 113... |
input [14:0] fe_mab; // Frontend Memory address bus
|
input [14:0] fe_mab; // Frontend Memory address bus
|
input fe_mb_en; // Frontend Memory bus enable
|
input fe_mb_en; // Frontend Memory bus enable
|
input mclk; // Main system clock
|
input mclk; // Main system clock
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] per_dout; // Peripheral data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input [15:0] pmem_dout; // Program Memory data output
|
input puc; // Main system reset
|
input puc_rst; // Main system reset
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
// 1) DECODER
|
// 1) DECODER
|
//=============================================================================
|
//=============================================================================
|
| Line 126... |
Line 126... |
//------------------
|
//------------------
|
|
|
// Execution unit access
|
// Execution unit access
|
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
|
wire eu_dmem_cen = ~(eu_mb_en & (eu_mab>=(`DMEM_BASE>>1)) &
|
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
|
(eu_mab<((`DMEM_BASE+`DMEM_SIZE)>>1)));
|
wire [15:0] eu_dmem_addr = eu_mab-(`DMEM_BASE>>1);
|
wire [15:0] eu_dmem_addr = {1'b0, eu_mab}-(`DMEM_BASE>>1);
|
|
|
// Debug interface access
|
// Debug interface access
|
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
|
wire dbg_dmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(`DMEM_BASE>>1)) &
|
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
|
(dbg_mem_addr[15:1]<((`DMEM_BASE+`DMEM_SIZE)>>1)));
|
wire [15:0] dbg_dmem_addr = dbg_mem_addr[15:1]-(`DMEM_BASE>>1);
|
wire [15:0] dbg_dmem_addr = {1'b0, dbg_mem_addr[15:1]}-(`DMEM_BASE>>1);
|
|
|
|
|
// RAM Interface
|
// RAM Interface
|
wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
|
wire [`DMEM_MSB:0] dmem_addr = ~dbg_dmem_cen ? dbg_dmem_addr[`DMEM_MSB:0] : eu_dmem_addr[`DMEM_MSB:0];
|
wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
|
wire dmem_cen = dbg_dmem_cen & eu_dmem_cen;
|
| Line 155... |
Line 155... |
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
|
wire fe_pmem_cen = ~(fe_mb_en & (fe_mab>=(PMEM_OFFSET>>1)));
|
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
|
wire [15:0] fe_pmem_addr = fe_mab-(PMEM_OFFSET>>1);
|
|
|
// Debug interface access
|
// Debug interface access
|
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
|
wire dbg_pmem_cen = ~(dbg_mem_en & (dbg_mem_addr[15:1]>=(PMEM_OFFSET>>1)));
|
wire [15:0] dbg_pmem_addr = dbg_mem_addr[15:1]-(PMEM_OFFSET>>1);
|
wire [15:0] dbg_pmem_addr = {1'b0, dbg_mem_addr[15:1]}-(PMEM_OFFSET>>1);
|
|
|
|
|
// ROM Interface (Execution unit has priority)
|
// ROM Interface (Execution unit has priority)
|
wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
|
wire [`PMEM_MSB:0] pmem_addr = ~dbg_pmem_cen ? dbg_pmem_addr[`PMEM_MSB:0] :
|
~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
|
~eu_pmem_cen ? eu_pmem_addr[`PMEM_MSB:0] : fe_pmem_addr[`PMEM_MSB:0];
|
| Line 170... |
Line 170... |
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
|
wire fe_pmem_wait = (~fe_pmem_cen & ~eu_pmem_cen);
|
|
|
|
|
// Peripherals
|
// Peripherals
|
//--------------------
|
//--------------------
|
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:9]==7'h00);
|
wire dbg_per_en = dbg_mem_en & (dbg_mem_addr[15:`PER_AWIDTH+1]=={15-`PER_AWIDTH{1'b0}});
|
wire eu_per_en = eu_mb_en & (eu_mab[14:8]==7'h00);
|
wire eu_per_en = eu_mb_en & (eu_mab[14:`PER_AWIDTH] =={15-`PER_AWIDTH{1'b0}});
|
|
|
wire [7:0] per_addr = dbg_mem_en ? dbg_mem_addr[8:1] : eu_mab[7:0];
|
|
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
|
wire [15:0] per_din = dbg_mem_en ? dbg_mem_dout : eu_mdb_out;
|
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
|
wire [1:0] per_we = dbg_mem_en ? dbg_mem_wr : eu_mb_wr;
|
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
|
wire per_en = dbg_mem_en ? dbg_per_en : eu_per_en;
|
|
wire [`PER_MSB:0] per_addr_mux = dbg_mem_en ? dbg_mem_addr[`PER_MSB+1:1] : eu_mab[`PER_MSB:0];
|
|
wire [14:0] per_addr_ful = {{15-`PER_AWIDTH{1'b0}}, per_addr_mux};
|
|
wire [13:0] per_addr = per_addr_ful[13:0];
|
|
|
reg [15:0] per_dout_val;
|
reg [15:0] per_dout_val;
|
always @ (posedge mclk or posedge puc)
|
always @ (posedge mclk or posedge puc_rst)
|
if (puc) per_dout_val <= 16'h0000;
|
if (puc_rst) per_dout_val <= 16'h0000;
|
else per_dout_val <= per_dout;
|
else per_dout_val <= per_dout;
|
|
|
|
|
// Frontend data Mux
|
// Frontend data Mux
|
//---------------------------------
|
//---------------------------------
|
// Whenever the frontend doesn't access the ROM, backup the data
|
// Whenever the frontend doesn't access the ROM, backup the data
|
|
|
// Detect whenever the data should be backuped and restored
|
// Detect whenever the data should be backuped and restored
|
reg fe_pmem_cen_dly;
|
reg fe_pmem_cen_dly;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) fe_pmem_cen_dly <= 1'b0;
|
if (puc_rst) fe_pmem_cen_dly <= 1'b0;
|
else fe_pmem_cen_dly <= fe_pmem_cen;
|
else fe_pmem_cen_dly <= fe_pmem_cen;
|
|
|
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
|
wire fe_pmem_save = ( fe_pmem_cen & ~fe_pmem_cen_dly) & ~dbg_halt_st;
|
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
|
wire fe_pmem_restore = (~fe_pmem_cen & fe_pmem_cen_dly) | dbg_halt_st;
|
|
|
reg [15:0] pmem_dout_bckup;
|
reg [15:0] pmem_dout_bckup;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) pmem_dout_bckup <= 16'h0000;
|
if (puc_rst) pmem_dout_bckup <= 16'h0000;
|
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
|
else if (fe_pmem_save) pmem_dout_bckup <= pmem_dout;
|
|
|
// Mux between the ROM data and the backup
|
// Mux between the ROM data and the backup
|
reg pmem_dout_bckup_sel;
|
reg pmem_dout_bckup_sel;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) pmem_dout_bckup_sel <= 1'b0;
|
if (puc_rst) pmem_dout_bckup_sel <= 1'b0;
|
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
|
else if (fe_pmem_save) pmem_dout_bckup_sel <= 1'b1;
|
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
|
else if (fe_pmem_restore) pmem_dout_bckup_sel <= 1'b0;
|
|
|
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
|
assign fe_mdb_in = pmem_dout_bckup_sel ? pmem_dout_bckup : pmem_dout;
|
|
|
| Line 217... |
Line 219... |
// Execution-Unit data Mux
|
// Execution-Unit data Mux
|
//---------------------------------
|
//---------------------------------
|
|
|
// Select between peripherals, RAM and ROM
|
// Select between peripherals, RAM and ROM
|
reg [1:0] eu_mdb_in_sel;
|
reg [1:0] eu_mdb_in_sel;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) eu_mdb_in_sel <= 2'b00;
|
if (puc_rst) eu_mdb_in_sel <= 2'b00;
|
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
|
else eu_mdb_in_sel <= {~eu_pmem_cen, per_en};
|
|
|
// Mux
|
// Mux
|
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
|
assign eu_mdb_in = eu_mdb_in_sel[1] ? pmem_dout :
|
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
|
eu_mdb_in_sel[0] ? per_dout_val : dmem_dout;
|
| Line 231... |
Line 233... |
//---------------------------------
|
//---------------------------------
|
|
|
// Select between peripherals, RAM and ROM
|
// Select between peripherals, RAM and ROM
|
`ifdef DBG_EN
|
`ifdef DBG_EN
|
reg [1:0] dbg_mem_din_sel;
|
reg [1:0] dbg_mem_din_sel;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) dbg_mem_din_sel <= 2'b00;
|
if (puc_rst) dbg_mem_din_sel <= 2'b00;
|
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
|
else dbg_mem_din_sel <= {~dbg_pmem_cen, dbg_per_en};
|
|
|
`else
|
`else
|
wire [1:0] dbg_mem_din_sel = 2'b00;
|
wire [1:0] dbg_mem_din_sel = 2'b00;
|
`endif
|
`endif
|
