| Line 142... |
Line 142... |
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// Read/Write vectors
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// Read/Write vectors
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
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wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
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// Masked input data for byte access
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wire [15:0] per_din_msk = per_din & {{8{per_we[1]}}, 8'hff};
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//============================================================================
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//============================================================================
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// 3) REGISTERS
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// 3) REGISTERS
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//============================================================================
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//============================================================================
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| Line 167... |
Line 169... |
`endif
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`endif
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always @ (posedge mclk_op1 or posedge puc_rst)
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always @ (posedge mclk_op1 or posedge puc_rst)
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if (puc_rst) op1 <= 16'h0000;
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if (puc_rst) op1 <= 16'h0000;
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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else op1 <= per_din;
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else op1 <= per_din_msk;
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`else
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`else
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else if (op1_wr) op1 <= per_din;
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else if (op1_wr) op1 <= per_din_msk;
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`endif
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`endif
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wire [15:0] op1_rd = op1;
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wire [15:0] op1_rd = op1;
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| Line 192... |
Line 194... |
`endif
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`endif
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always @ (posedge mclk_op2 or posedge puc_rst)
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always @ (posedge mclk_op2 or posedge puc_rst)
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if (puc_rst) op2 <= 16'h0000;
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if (puc_rst) op2 <= 16'h0000;
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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else op2 <= per_din;
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else op2 <= per_din_msk;
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`else
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`else
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else if (op2_wr) op2 <= per_din;
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else if (op2_wr) op2 <= per_din_msk;
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`endif
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`endif
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wire [15:0] op2_rd = op2;
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wire [15:0] op2_rd = op2;
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| Line 218... |
Line 220... |
wire mclk_reslo = mclk;
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wire mclk_reslo = mclk;
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`endif
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`endif
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always @ (posedge mclk_reslo or posedge puc_rst)
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always @ (posedge mclk_reslo or posedge puc_rst)
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if (puc_rst) reslo <= 16'h0000;
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if (puc_rst) reslo <= 16'h0000;
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else if (reslo_wr) reslo <= per_din;
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else if (reslo_wr) reslo <= per_din_msk;
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else if (result_clr) reslo <= 16'h0000;
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else if (result_clr) reslo <= 16'h0000;
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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else reslo <= reslo_nxt;
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else reslo <= reslo_nxt;
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`else
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`else
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else if (result_wr) reslo <= reslo_nxt;
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else if (result_wr) reslo <= reslo_nxt;
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| Line 247... |
Line 249... |
wire mclk_reshi = mclk;
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wire mclk_reshi = mclk;
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`endif
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`endif
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always @ (posedge mclk_reshi or posedge puc_rst)
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always @ (posedge mclk_reshi or posedge puc_rst)
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if (puc_rst) reshi <= 16'h0000;
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if (puc_rst) reshi <= 16'h0000;
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else if (reshi_wr) reshi <= per_din;
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else if (reshi_wr) reshi <= per_din_msk;
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else if (result_clr) reshi <= 16'h0000;
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else if (result_clr) reshi <= 16'h0000;
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`ifdef CLOCK_GATING
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`ifdef CLOCK_GATING
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else reshi <= reshi_nxt;
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else reshi <= reshi_nxt;
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`else
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`else
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else if (result_wr) reshi <= reshi_nxt;
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else if (result_wr) reshi <= reshi_nxt;
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