| Line 29... |
Line 29... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 104 $
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// $Rev: 111 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
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// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 59... |
Line 59... |
inst_bw, // Decoded Inst: byte width
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inst_bw, // Decoded Inst: byte width
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inst_dest, // Register destination selection
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inst_dest, // Register destination selection
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inst_src, // Register source selection
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inst_src, // Register source selection
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mclk, // Main system clock
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mclk, // Main system clock
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pc, // Program counter
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pc, // Program counter
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puc, // Main system reset
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puc_rst, // Main system reset
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reg_dest_val, // Selected register destination value
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reg_dest_val, // Selected register destination value
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reg_dest_wr, // Write selected register destination
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reg_dest_wr, // Write selected register destination
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reg_pc_call, // Trigger PC update for a CALL instruction
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reg_pc_call, // Trigger PC update for a CALL instruction
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reg_sp_val, // Stack Pointer next value
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reg_sp_val, // Stack Pointer next value
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reg_sp_wr, // Stack Pointer write
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reg_sp_wr, // Stack Pointer write
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| Line 91... |
Line 91... |
input inst_bw; // Decoded Inst: byte width
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input inst_bw; // Decoded Inst: byte width
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input [15:0] inst_dest; // Register destination selection
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input [15:0] inst_dest; // Register destination selection
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input [15:0] inst_src; // Register source selection
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input [15:0] inst_src; // Register source selection
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input mclk; // Main system clock
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input mclk; // Main system clock
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input [15:0] pc; // Program counter
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input [15:0] pc; // Program counter
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input puc; // Main system reset
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input puc_rst; // Main system reset
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input [15:0] reg_dest_val; // Selected register destination value
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input [15:0] reg_dest_val; // Selected register destination value
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input reg_dest_wr; // Write selected register destination
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input reg_dest_wr; // Write selected register destination
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input reg_pc_call; // Trigger PC update for a CALL instruction
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input reg_pc_call; // Trigger PC update for a CALL instruction
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input [15:0] reg_sp_val; // Stack Pointer next value
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input [15:0] reg_sp_val; // Stack Pointer next value
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input reg_sp_wr; // Stack Pointer write
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input reg_sp_wr; // Stack Pointer write
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| Line 137... |
Line 137... |
//-------------------
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//-------------------
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reg [15:0] r1;
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reg [15:0] r1;
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wire r1_wr = inst_dest[1] & reg_dest_wr;
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wire r1_wr = inst_dest[1] & reg_dest_wr;
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wire r1_inc = inst_src_in[1] & reg_incr;
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wire r1_inc = inst_src_in[1] & reg_incr;
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|
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r1 <= 16'h0000;
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if (puc_rst) r1 <= 16'h0000;
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else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe;
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else if (r1_wr) r1 <= reg_dest_val_in & 16'hfffe;
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else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe;
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else if (reg_sp_wr) r1 <= reg_sp_val & 16'hfffe;
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else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
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else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
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|
|
|
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| Line 164... |
Line 164... |
|
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wire r2_v = alu_stat_wr[3] ? alu_stat[3] :
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wire r2_v = alu_stat_wr[3] ? alu_stat[3] :
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r2_wr ? reg_dest_val_in[8] : r2[8]; // V
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r2_wr ? reg_dest_val_in[8] : r2[8]; // V
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|
|
|
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r2 <= 16'h0000;
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if (puc_rst) r2 <= 16'h0000;
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else if (reg_sr_clr) r2 <= 16'h0000;
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else if (reg_sr_clr) r2 <= 16'h0000;
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else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c};
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else r2 <= {7'h00, r2_v, r2_nxt, r2_n, r2_z, r2_c};
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|
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assign status = {r2[8], r2[2:0]};
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assign status = {r2[8], r2[2:0]};
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assign gie = r2[3];
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assign gie = r2[3];
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| Line 182... |
Line 182... |
//------------------------
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//------------------------
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reg [15:0] r3;
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reg [15:0] r3;
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wire r3_wr = inst_dest[3] & reg_dest_wr;
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wire r3_wr = inst_dest[3] & reg_dest_wr;
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wire r3_inc = inst_src_in[3] & reg_incr;
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wire r3_inc = inst_src_in[3] & reg_incr;
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|
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r3 <= 16'h0000;
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if (puc_rst) r3 <= 16'h0000;
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else if (r3_wr) r3 <= reg_dest_val_in;
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else if (r3_wr) r3 <= reg_dest_val_in;
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else if (r3_inc) r3 <= reg_incr_val;
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else if (r3_inc) r3 <= reg_incr_val;
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|
|
|
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//=============================================================================
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//=============================================================================
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| Line 196... |
Line 196... |
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// R4
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// R4
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reg [15:0] r4;
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reg [15:0] r4;
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wire r4_wr = inst_dest[4] & reg_dest_wr;
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wire r4_wr = inst_dest[4] & reg_dest_wr;
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wire r4_inc = inst_src_in[4] & reg_incr;
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wire r4_inc = inst_src_in[4] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r4 <= 16'h0000;
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if (puc_rst) r4 <= 16'h0000;
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else if (r4_wr) r4 <= reg_dest_val_in;
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else if (r4_wr) r4 <= reg_dest_val_in;
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else if (r4_inc) r4 <= reg_incr_val;
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else if (r4_inc) r4 <= reg_incr_val;
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|
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// R5
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// R5
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reg [15:0] r5;
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reg [15:0] r5;
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wire r5_wr = inst_dest[5] & reg_dest_wr;
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wire r5_wr = inst_dest[5] & reg_dest_wr;
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wire r5_inc = inst_src_in[5] & reg_incr;
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wire r5_inc = inst_src_in[5] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r5 <= 16'h0000;
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if (puc_rst) r5 <= 16'h0000;
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else if (r5_wr) r5 <= reg_dest_val_in;
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else if (r5_wr) r5 <= reg_dest_val_in;
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else if (r5_inc) r5 <= reg_incr_val;
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else if (r5_inc) r5 <= reg_incr_val;
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|
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// R6
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// R6
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reg [15:0] r6;
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reg [15:0] r6;
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wire r6_wr = inst_dest[6] & reg_dest_wr;
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wire r6_wr = inst_dest[6] & reg_dest_wr;
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wire r6_inc = inst_src_in[6] & reg_incr;
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wire r6_inc = inst_src_in[6] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r6 <= 16'h0000;
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if (puc_rst) r6 <= 16'h0000;
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else if (r6_wr) r6 <= reg_dest_val_in;
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else if (r6_wr) r6 <= reg_dest_val_in;
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else if (r6_inc) r6 <= reg_incr_val;
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else if (r6_inc) r6 <= reg_incr_val;
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|
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// R7
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// R7
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reg [15:0] r7;
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reg [15:0] r7;
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wire r7_wr = inst_dest[7] & reg_dest_wr;
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wire r7_wr = inst_dest[7] & reg_dest_wr;
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wire r7_inc = inst_src_in[7] & reg_incr;
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wire r7_inc = inst_src_in[7] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r7 <= 16'h0000;
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if (puc_rst) r7 <= 16'h0000;
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else if (r7_wr) r7 <= reg_dest_val_in;
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else if (r7_wr) r7 <= reg_dest_val_in;
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else if (r7_inc) r7 <= reg_incr_val;
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else if (r7_inc) r7 <= reg_incr_val;
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|
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// R8
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// R8
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reg [15:0] r8;
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reg [15:0] r8;
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wire r8_wr = inst_dest[8] & reg_dest_wr;
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wire r8_wr = inst_dest[8] & reg_dest_wr;
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wire r8_inc = inst_src_in[8] & reg_incr;
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wire r8_inc = inst_src_in[8] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r8 <= 16'h0000;
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if (puc_rst) r8 <= 16'h0000;
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else if (r8_wr) r8 <= reg_dest_val_in;
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else if (r8_wr) r8 <= reg_dest_val_in;
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else if (r8_inc) r8 <= reg_incr_val;
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else if (r8_inc) r8 <= reg_incr_val;
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|
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// R9
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// R9
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reg [15:0] r9;
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reg [15:0] r9;
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wire r9_wr = inst_dest[9] & reg_dest_wr;
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wire r9_wr = inst_dest[9] & reg_dest_wr;
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wire r9_inc = inst_src_in[9] & reg_incr;
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wire r9_inc = inst_src_in[9] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r9 <= 16'h0000;
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if (puc_rst) r9 <= 16'h0000;
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else if (r9_wr) r9 <= reg_dest_val_in;
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else if (r9_wr) r9 <= reg_dest_val_in;
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else if (r9_inc) r9 <= reg_incr_val;
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else if (r9_inc) r9 <= reg_incr_val;
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|
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// R10
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// R10
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reg [15:0] r10;
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reg [15:0] r10;
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wire r10_wr = inst_dest[10] & reg_dest_wr;
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wire r10_wr = inst_dest[10] & reg_dest_wr;
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wire r10_inc = inst_src_in[10] & reg_incr;
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wire r10_inc = inst_src_in[10] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r10 <= 16'h0000;
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if (puc_rst) r10 <= 16'h0000;
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else if (r10_wr) r10 <= reg_dest_val_in;
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else if (r10_wr) r10 <= reg_dest_val_in;
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else if (r10_inc) r10 <= reg_incr_val;
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else if (r10_inc) r10 <= reg_incr_val;
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|
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// R11
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// R11
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reg [15:0] r11;
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reg [15:0] r11;
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wire r11_wr = inst_dest[11] & reg_dest_wr;
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wire r11_wr = inst_dest[11] & reg_dest_wr;
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wire r11_inc = inst_src_in[11] & reg_incr;
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wire r11_inc = inst_src_in[11] & reg_incr;
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always @(posedge mclk or posedge puc)
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always @(posedge mclk or posedge puc_rst)
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if (puc) r11 <= 16'h0000;
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if (puc_rst) r11 <= 16'h0000;
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else if (r11_wr) r11 <= reg_dest_val_in;
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else if (r11_wr) r11 <= reg_dest_val_in;
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else if (r11_inc) r11 <= reg_incr_val;
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else if (r11_inc) r11 <= reg_incr_val;
|
|
|
// R12
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// R12
|
reg [15:0] r12;
|
reg [15:0] r12;
|
wire r12_wr = inst_dest[12] & reg_dest_wr;
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wire r12_wr = inst_dest[12] & reg_dest_wr;
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wire r12_inc = inst_src_in[12] & reg_incr;
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wire r12_inc = inst_src_in[12] & reg_incr;
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always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) r12 <= 16'h0000;
|
if (puc_rst) r12 <= 16'h0000;
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else if (r12_wr) r12 <= reg_dest_val_in;
|
else if (r12_wr) r12 <= reg_dest_val_in;
|
else if (r12_inc) r12 <= reg_incr_val;
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else if (r12_inc) r12 <= reg_incr_val;
|
|
|
// R13
|
// R13
|
reg [15:0] r13;
|
reg [15:0] r13;
|
wire r13_wr = inst_dest[13] & reg_dest_wr;
|
wire r13_wr = inst_dest[13] & reg_dest_wr;
|
wire r13_inc = inst_src_in[13] & reg_incr;
|
wire r13_inc = inst_src_in[13] & reg_incr;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) r13 <= 16'h0000;
|
if (puc_rst) r13 <= 16'h0000;
|
else if (r13_wr) r13 <= reg_dest_val_in;
|
else if (r13_wr) r13 <= reg_dest_val_in;
|
else if (r13_inc) r13 <= reg_incr_val;
|
else if (r13_inc) r13 <= reg_incr_val;
|
|
|
// R14
|
// R14
|
reg [15:0] r14;
|
reg [15:0] r14;
|
wire r14_wr = inst_dest[14] & reg_dest_wr;
|
wire r14_wr = inst_dest[14] & reg_dest_wr;
|
wire r14_inc = inst_src_in[14] & reg_incr;
|
wire r14_inc = inst_src_in[14] & reg_incr;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) r14 <= 16'h0000;
|
if (puc_rst) r14 <= 16'h0000;
|
else if (r14_wr) r14 <= reg_dest_val_in;
|
else if (r14_wr) r14 <= reg_dest_val_in;
|
else if (r14_inc) r14 <= reg_incr_val;
|
else if (r14_inc) r14 <= reg_incr_val;
|
|
|
// R15
|
// R15
|
reg [15:0] r15;
|
reg [15:0] r15;
|
wire r15_wr = inst_dest[15] & reg_dest_wr;
|
wire r15_wr = inst_dest[15] & reg_dest_wr;
|
wire r15_inc = inst_src_in[15] & reg_incr;
|
wire r15_inc = inst_src_in[15] & reg_incr;
|
always @(posedge mclk or posedge puc)
|
always @(posedge mclk or posedge puc_rst)
|
if (puc) r15 <= 16'h0000;
|
if (puc_rst) r15 <= 16'h0000;
|
else if (r15_wr) r15 <= reg_dest_val_in;
|
else if (r15_wr) r15 <= reg_dest_val_in;
|
else if (r15_inc) r15 <= reg_incr_val;
|
else if (r15_inc) r15 <= reg_incr_val;
|
|
|
|
|
//=============================================================================
|
//=============================================================================
|
