| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 181 $
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// $Rev: 202 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2013-02-25 22:24:10 +0100 (Mon, 25 Feb 2013) $
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// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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`endif
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`endif
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| Line 153... |
Line 153... |
wire r1_en = r1_wr | reg_sp_wr | r1_inc;
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wire r1_en = r1_wr | reg_sp_wr | r1_inc;
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wire mclk_r1;
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wire mclk_r1;
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omsp_clock_gate clock_gate_r1 (.gclk(mclk_r1),
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omsp_clock_gate clock_gate_r1 (.gclk(mclk_r1),
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.clk (mclk), .enable(r1_en), .scan_enable(scan_enable));
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.clk (mclk), .enable(r1_en), .scan_enable(scan_enable));
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`else
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`else
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wire UNUSED_scan_enable = scan_enable;
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wire mclk_r1 = mclk;
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wire mclk_r1 = mclk;
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`endif
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`endif
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always @(posedge mclk_r1 or posedge puc_rst)
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always @(posedge mclk_r1 or posedge puc_rst)
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if (puc_rst) r1 <= 16'h0000;
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if (puc_rst) r1 <= 16'h0000;
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Line 167... |
else r1 <= reg_incr_val & 16'hfffe;
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else r1 <= reg_incr_val & 16'hfffe;
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`else
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`else
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else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
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else if (r1_inc) r1 <= reg_incr_val & 16'hfffe;
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`endif
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`endif
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wire UNUSED_reg_sp_val_0 = reg_sp_val[0];
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// R2: Status register
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// R2: Status register
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//---------------------
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//---------------------
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reg [15:0] r2;
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reg [15:0] r2;
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wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
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wire r2_wr = (inst_dest[2] & reg_dest_wr) | reg_sr_wr;
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