| Line 29... |
Line 29... |
//
|
//
|
// *Author(s):
|
// *Author(s):
|
// - Olivier Girard, olgirard@gmail.com
|
// - Olivier Girard, olgirard@gmail.com
|
//
|
//
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
// $Rev: 104 $
|
// $Rev: 109 $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedBy: olivier.girard $
|
// $LastChangedDate: 2011-03-06 21:02:27 +0100 (Sun, 06 Mar 2011) $
|
// $LastChangedDate: 2011-03-27 13:49:47 +0200 (Sun, 27 Mar 2011) $
|
//----------------------------------------------------------------------------
|
//----------------------------------------------------------------------------
|
`ifdef OMSP_NO_INCLUDE
|
`ifdef OMSP_NO_INCLUDE
|
`else
|
`else
|
`include "openMSP430_defines.v"
|
`include "openMSP430_defines.v"
|
`endif
|
`endif
|
| Line 56... |
Line 56... |
nmi, // Non-maskable interrupt (asynchronous)
|
nmi, // Non-maskable interrupt (asynchronous)
|
nmie, // Non-maskable interrupt enable
|
nmie, // Non-maskable interrupt enable
|
per_addr, // Peripheral address
|
per_addr, // Peripheral address
|
per_din, // Peripheral data input
|
per_din, // Peripheral data input
|
per_en, // Peripheral enable (high active)
|
per_en, // Peripheral enable (high active)
|
per_wen, // Peripheral write enable (high active)
|
per_we, // Peripheral write enable (high active)
|
puc, // Main system reset
|
puc, // Main system reset
|
smclk_en, // SMCLK enable
|
smclk_en, // SMCLK enable
|
wdtie // Watchdog timer interrupt enable
|
wdtie // Watchdog timer interrupt enable
|
);
|
);
|
|
|
| Line 80... |
Line 80... |
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmi; // Non-maskable interrupt (asynchronous)
|
input nmie; // Non-maskable interrupt enable
|
input nmie; // Non-maskable interrupt enable
|
input [7:0] per_addr; // Peripheral address
|
input [7:0] per_addr; // Peripheral address
|
input [15:0] per_din; // Peripheral data input
|
input [15:0] per_din; // Peripheral data input
|
input per_en; // Peripheral enable (high active)
|
input per_en; // Peripheral enable (high active)
|
input [1:0] per_wen; // Peripheral write enable (high active)
|
input [1:0] per_we; // Peripheral write enable (high active)
|
input puc; // Main system reset
|
input puc; // Main system reset
|
input smclk_en; // SMCLK enable
|
input smclk_en; // SMCLK enable
|
input wdtie; // Watchdog timer interrupt enable
|
input wdtie; // Watchdog timer interrupt enable
|
|
|
|
|
| Line 111... |
Line 111... |
WDTCTL : reg_dec = WDTCTL_D;
|
WDTCTL : reg_dec = WDTCTL_D;
|
default: reg_dec = {512{1'b0}};
|
default: reg_dec = {512{1'b0}};
|
endcase
|
endcase
|
|
|
// Read/Write probes
|
// Read/Write probes
|
wire reg_write = |per_wen & per_en;
|
wire reg_write = |per_we & per_en;
|
wire reg_read = ~|per_wen & per_en;
|
wire reg_read = ~|per_we & per_en;
|
|
|
// Read/Write vectors
|
// Read/Write vectors
|
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
|
wire [511:0] reg_wr = reg_dec & {512{reg_write}};
|
wire [511:0] reg_rd = reg_dec & {512{reg_read}};
|
wire [511:0] reg_rd = reg_dec & {512{reg_read}};
|
|
|
