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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 2 and 17

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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
// $Rev: 17 $
 
// $LastChangedBy: olivier.girard $
 
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
 
//----------------------------------------------------------------------------
`timescale 1ns / 100ps
`timescale 1ns / 100ps
 
 
module  openMSP430 (
module  openMSP430 (
 
 
// OUTPUTs
// OUTPUTs

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