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//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 37 $
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// $Rev: 54 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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// $LastChangedDate: 2010-01-27 19:25:43 +0100 (Wed, 27 Jan 2010) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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module openMSP430 (
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module openMSP430 (
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Line 186... |
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omsp_frontend frontend_0 (
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omsp_frontend frontend_0 (
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// OUTPUTs
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// OUTPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.decode (decode), // Frontend decode instruction
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.e_state (e_state), // Execution state
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.e_state (e_state), // Execution state
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.exec_done (exec_done), // Execution completed
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.exec_done (exec_done), // Execution completed
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_as (inst_as), // Decoded Inst: source addressing mode
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.inst_alu (inst_alu), // ALU control signals
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.inst_alu (inst_alu), // ALU control signals
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// INPUTs
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// INPUTs
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
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.decode (decode), // Frontend decode instruction
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.decode_noirq (decode_noirq), // Frontend decode instruction
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mab (eu_mab), // Execution-Unit Memory address bus
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
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.eu_mdb_in (eu_mdb_in), // Memory data bus input
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
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.eu_mdb_out (eu_mdb_out), // Memory data bus output
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