URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430.v] - Diff between revs 71 and 86

Rev 71	Rev 86
Line 29...	Line 29...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 71 $`	`// $Rev: 86 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2010-03-07 21:14:33 +0100 (Sun, 07 Mar 2010) $`	`// $LastChangedDate: 2011-01-28 23:53:28 +0100 (Fri, 28 Jan 2011) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`include "timescale.v"	`include "timescale.v"
`include "openMSP430_defines.v"	`include "openMSP430_defines.v"

`module openMSP430 (`	`module openMSP430 (`
Line 137...	Line 137...
`wire [15:0] pc_sw;`	`wire [15:0] pc_sw;`
`wire [7:0] inst_jmp;`	`wire [7:0] inst_jmp;`
`wire [15:0] pc;`	`wire [15:0] pc;`
`wire [15:0] pc_nxt;`	`wire [15:0] pc_nxt;`

	`wire dbg_halt_cmd;`
	`wire dbg_mem_en;`
	`wire dbg_reg_wr;`
	`wire dbg_reset;`
`wire [15:0] dbg_mem_addr;`	`wire [15:0] dbg_mem_addr;`
`wire [15:0] dbg_mem_dout;`	`wire [15:0] dbg_mem_dout;`
`wire [15:0] dbg_mem_din;`	`wire [15:0] dbg_mem_din;`
`wire [15:0] dbg_reg_din;`	`wire [15:0] dbg_reg_din;`
`wire [1:0] dbg_mem_wr;`	`wire [1:0] dbg_mem_wr;`