| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 151 $
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// $Rev: 155 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-07-23 00:24:11 +0200 (Mon, 23 Jul 2012) $
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// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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//`define OMSP_NO_INCLUDE
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//`define OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`ifdef OMSP_NO_INCLUDE
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`else
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`else
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`include "openMSP430_undefines.v"
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`include "openMSP430_undefines.v"
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| Line 203... |
Line 203... |
// you are doing :-P
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// you are doing :-P
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//
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//
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//============================================================================
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//============================================================================
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//-------------------------------------------------------
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//-------------------------------------------------------
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// Select serial debug interface protocol
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//-------------------------------------------------------
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// DBG_UART -> Enable UART (8N1) debug interface
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// DBG_I2C -> Enable I2C debug interface
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//-------------------------------------------------------
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`define DBG_UART
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//`define DBG_I2C
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//-------------------------------------------------------
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// Enable the I2C broadcast address
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//-------------------------------------------------------
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// For multicore systems, a common I2C broadcast address
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// can be given to all oMSP cores in order to
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// synchronously RESET, START, STOP, or STEP all CPUs
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// at once with a single I2C command.
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// If you have a single openMSP430 in your system,
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// this option can stay commented-out.
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//-------------------------------------------------------
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//`define DBG_I2C_BROADCAST
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//-------------------------------------------------------
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// Number of hardware breakpoint/watchpoint units
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// Number of hardware breakpoint/watchpoint units
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// (each unit contains two hardware addresses available
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// (each unit contains two hardware addresses available
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// for breakpoints or watchpoints):
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// for breakpoints or watchpoints):
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
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| Line 773... |
Line 796... |
//`define DBG_UART_BAUD 921600
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//`define DBG_UART_BAUD 921600
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`define DBG_UART_BAUD 2000000
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`define DBG_UART_BAUD 2000000
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`define DBG_DCO_FREQ 20000000
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`define DBG_DCO_FREQ 20000000
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`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
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`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
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// Debug interface selection
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// `define DBG_UART -> Enable UART (8N1) debug interface
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// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
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//
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`define DBG_UART
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//`define DBG_JTAG
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// Debug interface input synchronizer
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// Debug interface input synchronizer
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`define SYNC_DBG_UART_RXD
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`define SYNC_DBG_UART_RXD
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|
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// Enable/Disable the hardware breakpoint RANGE mode
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// Enable/Disable the hardware breakpoint RANGE mode
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`ifdef DBG_HWBRK_RANGE
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`ifdef DBG_HWBRK_RANGE
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| Line 796... |
Line 812... |
`define DBG_UART_XFER_CNT_W 16
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`define DBG_UART_XFER_CNT_W 16
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|
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// Check configuration
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// Check configuration
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`ifdef DBG_EN
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`ifdef DBG_EN
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`ifdef DBG_UART
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`ifdef DBG_UART
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`ifdef DBG_JTAG
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`ifdef DBG_I2C
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CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
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CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
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`endif
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`endif
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`else
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`else
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`ifdef DBG_JTAG
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`ifdef DBG_I2C
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CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
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`else
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`else
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CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
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CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
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`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
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//
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//
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