URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Diff between revs 202 and 204

Rev 202	Rev 204
Line 34...	Line 34...
`//`	`//`
`// *Author(s):`	`// *Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
`// $Rev: 202 $`	`// $Rev: 204 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $`	`// $LastChangedDate: 2015-07-08 22:34:10 +0200 (Wed, 08 Jul 2015) $`
`//----------------------------------------------------------------------------`	`//----------------------------------------------------------------------------`
//`define OMSP_NO_INCLUDE	//`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE	`ifdef OMSP_NO_INCLUDE
`else	`else
`include "openMSP430_undefines.v"	`include "openMSP430_undefines.v"
Line 782...	Line 782...
`define BRK_RANGE 4	`define BRK_RANGE 4

`// Basic clock module: BCSCTL1 Control Register`	`// Basic clock module: BCSCTL1 Control Register`
`define DIVAx 5:4	`define DIVAx 5:4
`define DMA_CPUOFF 0	`define DMA_CPUOFF 0
`define DMA_SCG0 1	`define DMA_OSCOFF 1
`define DMA_SCG1 2	`define DMA_SCG0 2
`define DMA_OSCOFF 3	`define DMA_SCG1 3

`// Basic clock module: BCSCTL2 Control Register`	`// Basic clock module: BCSCTL2 Control Register`
`define SELMx 7	`define SELMx 7
`define DIVMx 5:4	`define DIVMx 5:4
`define SELS 3	`define SELS 3