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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_defines.v] - Diff between revs 17 and 23

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`ifdef OPENMSP430_DEFINES
 
`else
 
`define OPENMSP430_DEFINES
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2001 Authors
//
//
// This source file may be used and distributed without restriction provided
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// that this copyright statement is not removed from the file and that any
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// along with this source; if not, write to the Free Software Foundation,
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 
// 
// *File Name: openMSP430.inc
// *File Name: openMSP430_defines.v
// 
// 
// *Module Description:
// *Module Description:
//                      openMSP430 Configuration file
//                      openMSP430 Configuration file
//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 17 $
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
// ROM Size:
// ROM Size:
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CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
   `endif
   `endif
 `endif
 `endif
`endif
`endif
 
 
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`endif
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