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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Diff between revs 111 and 136

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//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
// Copyright (C) 2009 , Olivier Girard
//
//
// This source file may be used and distributed without restriction provided
// Redistribution and use in source and binary forms, with or without
// that this copyright statement is not removed from the file and that any
// modification, are permitted provided that the following conditions
// derivative work contains the original copyright notice and the associated
// are met:
// disclaimer.
//     * Redistributions of source code must retain the above copyright
 
//       notice, this list of conditions and the following disclaimer.
 
//     * Redistributions in binary form must reproduce the above copyright
 
//       notice, this list of conditions and the following disclaimer in the
 
//       documentation and/or other materials provided with the distribution.
 
//     * Neither the name of the authors nor the names of its contributors
 
//       may be used to endorse or promote products derived from this software
 
//       without specific prior written permission.
//
//
// This source file is free software; you can redistribute it and/or modify
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// it under the terms of the GNU Lesser General Public License as published
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// by the Free Software Foundation; either version 2.1 of the License, or
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// (at your option) any later version.
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
//
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// This source is distributed in the hope that it will be useful, but WITHOUT
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// License for more details.
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// You should have received a copy of the GNU Lesser General Public License
// THE POSSIBILITY OF SUCH DAMAGE
// along with this source; if not, write to the Free Software Foundation,
 
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 
// 
// *File Name: openMSP430_undefines.v
// *File Name: openMSP430_undefines.v
// 
// 
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// Custom user version number
// Custom user version number
`ifdef USER_VERSION
`ifdef USER_VERSION
`undef USER_VERSION
`undef USER_VERSION
`endif
`endif
 
 
 
// Include/Exclude Watchdog timer
 
`ifdef WATCHDOG
 
`undef WATCHDOG
 
`endif
 
 
 
// Include/Exclude Non-Maskable-Interrupt support
 
`ifdef NMI
 
`undef NMI
 
`endif
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
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`endif
`endif
`ifdef SYNC_NMI
`ifdef SYNC_NMI
`undef SYNC_NMI
`undef SYNC_NMI
`endif
`endif
 
 
 
// ASIC version
 
`ifdef ASIC
 
`undef ASIC
 
`endif
 
 
 
 
 
//----------------------------------------------------------------------------
 
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
 
//----------------------------------------------------------------------------
 
 
 
// Fine grained clock gating
 
`ifdef CLOCK_GATING
 
`undef CLOCK_GATING
 
`endif
 
 
 
// LFXT clock domain
 
`ifdef LFXT_DOMAIN
 
`undef LFXT_DOMAIN
 
`endif
 
 
 
// MCLK: Clock Mux
 
`ifdef MCLK_MUX
 
`undef MCLK_MUX
 
`endif
 
 
 
// SMCLK: Clock Mux
 
`ifdef SMCLK_MUX
 
`undef SMCLK_MUX
 
`endif
 
 
 
// WATCHDOG: Clock Mux
 
`ifdef WATCHDOG_MUX
 
`undef WATCHDOG_MUX
 
`endif
 
 
 
// MCLK: Clock divider
 
`ifdef MCLK_DIVIDER
 
`undef MCLK_DIVIDER
 
`endif
 
 
 
// SMCLK: Clock divider (/1/2/4/8)
 
`ifdef SMCLK_DIVIDER
 
`undef SMCLK_DIVIDER
 
`endif
 
 
 
// ACLK: Clock divider (/1/2/4/8)
 
`ifdef ACLK_DIVIDER
 
`undef ACLK_DIVIDER
 
`endif
 
 
 
// LOW POWER MODE: CPUOFF
 
`ifdef CPUOFF_EN
 
`undef CPUOFF_EN
 
`endif
 
 
 
// LOW POWER MODE: OSCOFF
 
`ifdef OSCOFF_EN
 
`undef OSCOFF_EN
 
`endif
 
 
 
// LOW POWER MODE: SCG0
 
`ifdef SCG0_EN
 
`undef SCG0_EN
 
`endif
 
 
 
// LOW POWER MODE: SCG1
 
`ifdef SCG1_EN
 
`undef SCG1_EN
 
`endif
 
 
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
Line 566... Line 650...
`ifdef DIVAx
`ifdef DIVAx
`undef DIVAx
`undef DIVAx
`endif
`endif
 
 
// Basic clock module: BCSCTL2 Control Register
// Basic clock module: BCSCTL2 Control Register
 
`ifdef SELMx
 
`undef SELMx
 
`endif
 
`ifdef DIVMx
 
`undef DIVMx
 
`endif
`ifdef SELS
`ifdef SELS
`undef SELS
`undef SELS
`endif
`endif
`ifdef DIVSx
`ifdef DIVSx
`undef DIVSx
`undef DIVSx
`endif
`endif
 
 
 
// MCLK Clock gate
 
`ifdef MCLK_CGATE
 
`undef MCLK_CGATE
 
`endif
 
 
 
// SMCLK Clock gate
 
`ifdef SMCLK_CGATE
 
`undef SMCLK_CGATE
 
`endif
 
 
//
//
// DEBUG INTERFACE EXTRA CONFIGURATION
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
//======================================
 
 

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