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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Diff between revs 155 and 181

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Rev 155 Rev 181
Line 261... Line 261...
 
 
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
 
// ASIC/FPGA-like clocking
 
`ifdef ASIC_CLOCKING
 
`undef ASIC_CLOCKING
 
`endif
 
 
// Fine grained clock gating
// Fine grained clock gating
`ifdef CLOCK_GATING
`ifdef CLOCK_GATING
`undef CLOCK_GATING
`undef CLOCK_GATING
`endif
`endif
 
 

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