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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Diff between revs 72 and 74

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Rev 72 Rev 74
Line 561... Line 561...
// Debug interface: Software breakpoint opcode
// Debug interface: Software breakpoint opcode
`ifdef DBG_SWBRK_OP
`ifdef DBG_SWBRK_OP
`undef DBG_SWBRK_OP
`undef DBG_SWBRK_OP
`endif
`endif
 
 
// Debug interface ID
 
`ifdef DBG_ID
 
`undef DBG_ID
 
`endif
 
 
 
// Debug UART interface auto data synchronization
// Debug UART interface auto data synchronization
`ifdef DBG_UART_AUTO_SYNC
`ifdef DBG_UART_AUTO_SYNC
`undef DBG_UART_AUTO_SYNC
`undef DBG_UART_AUTO_SYNC
`endif
`endif
 
 
Line 587... Line 582...
// Enable/Disable the hardware breakpoint RANGE mode
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef HWBRK_RANGE
`ifdef HWBRK_RANGE
`undef HWBRK_RANGE
`undef HWBRK_RANGE
`endif
`endif
 
 
 
// Counter width for the debug interface UART
 
`ifdef DBG_UART_XFER_CNT_W
 
`undef DBG_UART_XFER_CNT_W
 
`endif
 
 
//
//
// MULTIPLIER CONFIGURATION
// MULTIPLIER CONFIGURATION
//======================================
//======================================
 
 
`ifdef MPY_16x16
`ifdef MPY_16x16

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