| Line 34... |
Line 34... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 74 $
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// $Rev: 85 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2010-08-28 21:53:08 +0200 (Sat, 28 Aug 2010) $
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// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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`include "timescale.v"
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`include "timescale.v"
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`include "openMSP430_defines.v"
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`include "openMSP430_defines.v"
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|
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module template_periph_8b (
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module template_periph_8b (
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Line 171... |
//============================================================================
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//============================================================================
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// 4) DATA OUTPUT GENERATION
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// 4) DATA OUTPUT GENERATION
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//============================================================================
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//============================================================================
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// Data output mux
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// Data output mux
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wire [15:0] cntrl1_rd = (cntrl1 & {8{reg_rd[CNTRL1/2]}}) << (8 & {4{CNTRL1[0]}});
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wire [15:0] cntrl1_rd = {8'h00, (cntrl1 & {8{reg_rd[CNTRL1/2]}})} << (8 & {4{CNTRL1[0]}});
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wire [15:0] cntrl2_rd = (cntrl2 & {8{reg_rd[CNTRL2/2]}}) << (8 & {4{CNTRL2[0]}});
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wire [15:0] cntrl2_rd = {8'h00, (cntrl2 & {8{reg_rd[CNTRL2/2]}})} << (8 & {4{CNTRL2[0]}});
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wire [15:0] cntrl3_rd = (cntrl3 & {8{reg_rd[CNTRL3/2]}}) << (8 & {4{CNTRL3[0]}});
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wire [15:0] cntrl3_rd = {8'h00, (cntrl3 & {8{reg_rd[CNTRL3/2]}})} << (8 & {4{CNTRL3[0]}});
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wire [15:0] cntrl4_rd = (cntrl4 & {8{reg_rd[CNTRL4/2]}}) << (8 & {4{CNTRL4[0]}});
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wire [15:0] cntrl4_rd = {8'h00, (cntrl4 & {8{reg_rd[CNTRL4/2]}})} << (8 & {4{CNTRL4[0]}});
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wire [15:0] per_dout = cntrl1_rd |
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wire [15:0] per_dout = cntrl1_rd |
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cntrl2_rd |
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cntrl2_rd |
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cntrl3_rd |
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cntrl3_rd |
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cntrl4_rd;
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cntrl4_rd;
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