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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [periph/] [template_periph_8b.v] - Diff between revs 111 and 136

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//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Copyright (C) 2009 Authors
// Copyright (C) 2009 , Olivier Girard
//
//
// Redistribution and use in source and binary forms, with or without
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// modification, are permitted provided that the following conditions
// are met:
// are met:
//     * Redistributions of source code must retain the above copyright
//     * Redistributions of source code must retain the above copyright
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//
//
// *Author(s):
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//              - Olivier Girard,    olgirard@gmail.com
//
//
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// $Rev: 111 $
// $Rev: 136 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
 
 
module  template_periph_8b (
module  template_periph_8b (
 
 
// OUTPUTs
// OUTPUTs
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                       CNTRL3      =  'h2,
                       CNTRL3      =  'h2,
                       CNTRL4      =  'h3;
                       CNTRL4      =  'h3;
 
 
 
 
// Register one-hot decoder utilities
// Register one-hot decoder utilities
parameter              DEC_SZ      =  2**DEC_WD;
parameter              DEC_SZ      =  (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
parameter [DEC_SZ-1:0] BASE_REG    =  {{DEC_SZ-1{1'b0}}, 1'b1};
 
 
// Register one-hot decoder
// Register one-hot decoder
parameter [DEC_SZ-1:0] CNTRL1_D  = (BASE_REG << CNTRL1),
parameter [DEC_SZ-1:0] CNTRL1_D  = (BASE_REG << CNTRL1),
                       CNTRL2_D  = (BASE_REG << CNTRL2),
                       CNTRL2_D  = (BASE_REG << CNTRL2),

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