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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [submit.f] - Diff between revs 111 and 136

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Rev 111 Rev 136
Line 26... Line 26...
//
//
// Author(s):
// Author(s):
//             - Olivier Girard,    olgirard@gmail.com
//             - Olivier Girard,    olgirard@gmail.com
//
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// $Rev: 111 $
// $Rev: 136 $
// $LastChangedBy: olivier.girard $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
// $LastChangedDate: 2012-03-22 22:14:16 +0100 (Thu, 22 Mar 2012) $
//=============================================================================
//=============================================================================
 
 
//=============================================================================
//=============================================================================
// Testbench related
// Testbench related
//=============================================================================
//=============================================================================
Line 59... Line 59...
 
 
+incdir+../../../rtl/verilog/
+incdir+../../../rtl/verilog/
../../../rtl/verilog/openMSP430_fpga.v
../../../rtl/verilog/openMSP430_fpga.v
../../../rtl/verilog/io_mux.v
../../../rtl/verilog/io_mux.v
../../../rtl/verilog/driver_7segment.v
../../../rtl/verilog/driver_7segment.v
 
../../../rtl/verilog/omsp_uart.v
../../../rtl/verilog/coregen/ram_8x512_hi.v
../../../rtl/verilog/coregen/ram_8x512_hi.v
../../../rtl/verilog/coregen/ram_8x512_lo.v
../../../rtl/verilog/coregen/ram_8x512_lo.v
../../../rtl/verilog/coregen/rom_8x2k_hi.v
../../../rtl/verilog/coregen/rom_8x2k_hi.v
../../../rtl/verilog/coregen/rom_8x2k_lo.v
../../../rtl/verilog/coregen/rom_8x2k_lo.v
 
 
Line 76... Line 77...
../../../rtl/verilog/openmsp430/openMSP430.v
../../../rtl/verilog/openmsp430/openMSP430.v
../../../rtl/verilog/openmsp430/omsp_frontend.v
../../../rtl/verilog/openmsp430/omsp_frontend.v
../../../rtl/verilog/openmsp430/omsp_execution_unit.v
../../../rtl/verilog/openmsp430/omsp_execution_unit.v
../../../rtl/verilog/openmsp430/omsp_register_file.v
../../../rtl/verilog/openmsp430/omsp_register_file.v
../../../rtl/verilog/openmsp430/omsp_alu.v
../../../rtl/verilog/openmsp430/omsp_alu.v
 
../../../rtl/verilog/openmsp430/omsp_sfr.v
../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
../../../rtl/verilog/openmsp430/omsp_clock_module.v
../../../rtl/verilog/openmsp430/omsp_clock_module.v
../../../rtl/verilog/openmsp430/omsp_sfr.v
 
../../../rtl/verilog/openmsp430/omsp_dbg.v
../../../rtl/verilog/openmsp430/omsp_dbg.v
../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
../../../rtl/verilog/openmsp430/omsp_watchdog.v
../../../rtl/verilog/openmsp430/omsp_watchdog.v
../../../rtl/verilog/openmsp430/omsp_multiplier.v
../../../rtl/verilog/openmsp430/omsp_multiplier.v
 
../../../rtl/verilog/openmsp430/omsp_sync_reset.v
../../../rtl/verilog/openmsp430/omsp_sync_cell.v
../../../rtl/verilog/openmsp430/omsp_sync_cell.v
 
../../../rtl/verilog/openmsp430/omsp_scan_mux.v
 
../../../rtl/verilog/openmsp430/omsp_and_gate.v
 
../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v
 
../../../rtl/verilog/openmsp430/omsp_clock_gate.v
 
../../../rtl/verilog/openmsp430/omsp_clock_mux.v
../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
 
 
 
 
 
 
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