| Line 26... |
Line 26... |
//
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//
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// Author(s):
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// Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// $Rev: 26 $
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// $Rev: 37 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2009-12-19 13:25:10 +0100 (Sat, 19 Dec 2009) $
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// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
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//=============================================================================
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//=============================================================================
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|
|
//=============================================================================
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//=============================================================================
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// Xilinx library
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// Xilinx library
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//=============================================================================
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//=============================================================================
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| Line 61... |
Line 61... |
// openMSP430
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// openMSP430
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//=============================================================================
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//=============================================================================
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|
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+incdir+../../../rtl/verilog/openmsp430/
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+incdir+../../../rtl/verilog/openmsp430/
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../../../rtl/verilog/openmsp430/openMSP430.v
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../../../rtl/verilog/openmsp430/openMSP430.v
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../../../rtl/verilog/openmsp430/frontend.v
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../../../rtl/verilog/openmsp430/omsp_frontend.v
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../../../rtl/verilog/openmsp430/execution_unit.v
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../../../rtl/verilog/openmsp430/omsp_execution_unit.v
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../../../rtl/verilog/openmsp430/register_file.v
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../../../rtl/verilog/openmsp430/omsp_register_file.v
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../../../rtl/verilog/openmsp430/alu.v
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../../../rtl/verilog/openmsp430/omsp_alu.v
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../../../rtl/verilog/openmsp430/mem_backbone.v
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../../../rtl/verilog/openmsp430/omsp_mem_backbone.v
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../../../rtl/verilog/openmsp430/clock_module.v
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../../../rtl/verilog/openmsp430/omsp_clock_module.v
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../../../rtl/verilog/openmsp430/sfr.v
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../../../rtl/verilog/openmsp430/omsp_sfr.v
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../../../rtl/verilog/openmsp430/dbg.v
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../../../rtl/verilog/openmsp430/omsp_dbg.v
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../../../rtl/verilog/openmsp430/dbg_hwbrk.v
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../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
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../../../rtl/verilog/openmsp430/dbg_uart.v
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../../../rtl/verilog/openmsp430/omsp_dbg_uart.v
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../../../rtl/verilog/openmsp430/watchdog.v
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../../../rtl/verilog/openmsp430/omsp_watchdog.v
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../../../rtl/verilog/openmsp430/periph/gpio.v
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../../../rtl/verilog/openmsp430/periph/omsp_gpio.v
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../../../rtl/verilog/openmsp430/periph/timerA.v
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../../../rtl/verilog/openmsp430/periph/omsp_timerA.v
|
|
|
|
|
//=============================================================================
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//=============================================================================
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// Testbench related
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// Testbench related
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//=============================================================================
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//=============================================================================
|
