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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [submit.f] - Diff between revs 71 and 85

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Rev 71	Rev 85
Line 26...	Line 26...
`//`	`//`
`// Author(s):`	`// Author(s):`
`// - Olivier Girard, olgirard@gmail.com`	`// - Olivier Girard, olgirard@gmail.com`
`//`	`//`
`//-----------------------------------------------------------------------------`	`//-----------------------------------------------------------------------------`
`// $Rev: 71 $`	`// $Rev: 85 $`
`// $LastChangedBy: olivier.girard $`	`// $LastChangedBy: olivier.girard $`
`// $LastChangedDate: 2010-03-07 21:14:33 +0100 (Sun, 07 Mar 2010) $`	`// $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $`
`//=============================================================================`	`//=============================================================================`

`//=============================================================================`	`//=============================================================================`
`// Xilinx library`	`// Xilinx library`
`//=============================================================================`	`//=============================================================================`
`+libext+.v`	`+libext+.v`

`-y /opt/Xilinx/10.1/ISE/verilog/src/unisims/`	`-y /opt/Xilinx/12.2/ISE_DS/ISE/verilog/src/unisims/`
`-y /opt/Xilinx/10.1/ISE/verilog/src/simprims/`	`-y /opt/Xilinx/12.2/ISE_DS/ISE/verilog/src/simprims/`
`-y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib/`	`-y /opt/Xilinx/12.2/ISE_DS/ISE/verilog/src/XilinxCoreLib/`


`//=============================================================================`	`//=============================================================================`
`// FPGA Specific modules`	`// FPGA Specific modules`
`//=============================================================================`	`//=============================================================================`

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] [src/] [submit.f] - Diff between revs 71 and 85