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//----------------------------------------------------------------------------
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// Copyright (C) 2001 Authors
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source; if not, write to the Free Software Foundation,
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// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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//
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//----------------------------------------------------------------------------
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//
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// *File Name: openMSP430_fpga.prj
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//
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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//
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//----------------------------------------------------------------------------
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// $Rev: 153 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-08-22 00:27:18 +0200 (Wed, 22 Aug 2012) $
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//----------------------------------------------------------------------------
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//=============================================================================
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// FPGA Specific modules
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//=============================================================================
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`include "../../../rtl/verilog/openMSP430_fpga.v"
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`include "../../../rtl/verilog/io_mux.v"
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`include "../../../rtl/verilog/driver_7segment.v"
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`include "../../../rtl/verilog/omsp_uart.v"
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`include "../../../rtl/verilog/coregen/ram_8x512_hi.v"
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`include "../../../rtl/verilog/coregen/ram_8x512_lo.v"
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`include "../../../rtl/verilog/coregen/rom_8x2k_hi.v"
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`include "../../../rtl/verilog/coregen/rom_8x2k_lo.v"
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//=============================================================================
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// openMSP430
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//=============================================================================
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`include "../../../rtl/verilog/openmsp430/openMSP430.v"
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`include "../../../rtl/verilog/openmsp430/omsp_frontend.v"
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`include "../../../rtl/verilog/openmsp430/omsp_execution_unit.v"
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`include "../../../rtl/verilog/openmsp430/omsp_register_file.v"
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`include "../../../rtl/verilog/openmsp430/omsp_alu.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sfr.v"
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`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
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`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
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`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
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`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
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`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"
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`include "../../../rtl/verilog/openmsp430/omsp_and_gate.v"
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`include "../../../rtl/verilog/openmsp430/omsp_wakeup_cell.v"
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`include "../../../rtl/verilog/openmsp430/omsp_clock_gate.v"
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`include "../../../rtl/verilog/openmsp430/omsp_clock_mux.v"
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`include "../../../rtl/verilog/openmsp430/periph/omsp_gpio.v"
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`include "../../../rtl/verilog/openmsp430/periph/omsp_timerA.v"
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