| Line 26... |
Line 26... |
//
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//
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// *Author(s):
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// *Author(s):
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// - Olivier Girard, olgirard@gmail.com
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// - Olivier Girard, olgirard@gmail.com
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//
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// $Rev: 153 $
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// $Rev: 155 $
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// $LastChangedBy: olivier.girard $
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// $LastChangedBy: olivier.girard $
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// $LastChangedDate: 2012-08-22 00:27:18 +0200 (Wed, 22 Aug 2012) $
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// $LastChangedDate: 2012-10-15 23:35:05 +0200 (Mon, 15 Oct 2012) $
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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|
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//=============================================================================
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//=============================================================================
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// FPGA Specific modules
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// FPGA Specific modules
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//=============================================================================
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//=============================================================================
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| Line 60... |
Line 60... |
`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
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`include "../../../rtl/verilog/openmsp430/omsp_mem_backbone.v"
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`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
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`include "../../../rtl/verilog/openmsp430/omsp_clock_module.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_hwbrk.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_uart.v"
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`include "../../../rtl/verilog/openmsp430/omsp_dbg_i2c.v"
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`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
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`include "../../../rtl/verilog/openmsp430/omsp_watchdog.v"
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`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
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`include "../../../rtl/verilog/openmsp430/omsp_multiplier.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_reset.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
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`include "../../../rtl/verilog/openmsp430/omsp_sync_cell.v"
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`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"
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`include "../../../rtl/verilog/openmsp430/omsp_scan_mux.v"
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