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https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
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Rev 153 |
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::######################################################
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::# #
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::# Xilinx Synthesis, Place & Route script for WINDOWS #
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::# #
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::######################################################
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:: Cleanup
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RMDIR /S /Q .\WORK
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MKDIR WORK
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cd ./WORK
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:: Copy the RAM & ROM ngc files
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XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_hi.ngc .
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XCOPY ..\..\..\rtl\verilog\coregen\ram_8x512_lo.ngc .
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XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_hi.ngc .
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XCOPY ..\..\..\rtl\verilog\coregen\rom_8x2k_lo.ngc .
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:: Copy the Xilinx constraints file
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XCOPY ..\scripts\openMSP430_fpga.ucf .
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:: Create link to the TimerA include file
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XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_defines.v .
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XCOPY ..\..\..\rtl\verilog\openmsp430\periph\omsp_timerA_undefines.v .
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:: XFLOW
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::---------------
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xflow -p 3S200FT256-4 -implement high_effort.opt ^
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-config bitgen.opt ^
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-synth ..\scripts\xst_verilog.opt ^
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..\scripts\openMSP430_fpga.prj
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:: MANUAL FLOW
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::---------------
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::xst -intstyle xflow -ifn ..\openMSP430_fpga.xst
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::ngdbuild -p xc3s200-4-ft256 -uc ..\openMSP430_fpga.ucf openMSP430_fpga
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::map -k 6 -detail -pr b openMSP430_fpga
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::par -ol med -w openMSP430_fpga.ncd openMSP430_fpga
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::trce -e -o openMSP430_fpga_err.twr openMSP430_fpga
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::trce -v -o openMSP430_fpga_ver.twr openMSP430_fpga
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::bitgen -w -g UserID:5555000 -g DonePipe:yes -g UnusedPin:Pullup openMSP430_fpga
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cd ..
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XCOPY .\WORK\openMSP430_fpga.bit .\bitstreams\.
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PAUSE
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