| Line 465... |
Line 465... |
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
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runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
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cpu_state.pc_delay);
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cpu_state.pc_delay);
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}
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}
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}
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}
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INSTRUCTION (l_jalr) {
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INSTRUCTION (l_jalr) {
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cpu_state.pc_delay = PARAM0;
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/* Badly aligned destination or use of link register triggers an exception */
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uorreg_t temp1 = PARAM0;
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|
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if (REG_PARAM0 == LINK_REGNO)
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{
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except_handle (EXCEPT_ILLEGAL, cpu_state.pc);
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}
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else if ((temp1 & 0x3) != 0)
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{
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except_handle (EXCEPT_ALIGN, cpu_state.pc);
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}
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else
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{
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cpu_state.pc_delay = temp1;
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setsim_reg(LINK_REGNO, cpu_state.pc + 8);
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setsim_reg(LINK_REGNO, cpu_state.pc + 8);
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next_delay_insn = 1;
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next_delay_insn = 1;
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}
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}
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}
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INSTRUCTION (l_jr) {
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INSTRUCTION (l_jr) {
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cpu_state.pc_delay = PARAM0;
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/* Badly aligned destination triggers an exception */
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uorreg_t temp1 = PARAM0;
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|
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if ((temp1 & 0x3) != 0)
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{
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except_handle (EXCEPT_ALIGN, cpu_state.pc);
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}
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else
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{
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cpu_state.pc_delay = temp1;
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next_delay_insn = 1;
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next_delay_insn = 1;
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|
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if (config.sim.profile)
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if (config.sim.profile)
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fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
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{
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cpu_state.pc_delay);
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fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n",
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runtime.sim.cycles, cpu_state.pc_delay);
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}
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}
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}
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}
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INSTRUCTION (l_rfe) {
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INSTRUCTION (l_rfe) {
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pcnext = cpu_state.sprs[SPR_EPCR_BASE];
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pcnext = cpu_state.sprs[SPR_EPCR_BASE];
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mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
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mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
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}
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}
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