URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc3/] [cpu/] [or1k/] [sprs.c] - Diff between revs 226 and 430

Rev 226	Rev 430
Line 152...	Line 152...
`}`	`}`
`}`	`}`
`break;`	`break;`
`case SPR_PICSR:`	`case SPR_PICSR:`
`if(!config.pic.edge_trigger)`	`if(!config.pic.edge_trigger)`
	`/* When configured with level triggered interrupts we clear PICSR in PIC`
	`when IRQ goes low */`
`cpu_state.sprs[SPR_PICSR] = prev_val;`	`cpu_state.sprs[SPR_PICSR] = prev_val;`
`break;`	`break;`
`case SPR_PICMR:`	`case SPR_PICMR:`
`if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)`	`if(cpu_state.sprs[SPR_SR] & SPR_SR_IEE)`
`pic_ints_en();`	`pic_ints_en();`