| Line 5... |
Line 5... |
int ic_enable_cmd (int argc, char *argv[])
|
int ic_enable_cmd (int argc, char *argv[])
|
{
|
{
|
unsigned long addr;
|
unsigned long addr;
|
unsigned long sr;
|
unsigned long sr;
|
|
|
if (argc) return -1;
|
if (argc)
|
|
return -1;
|
/* Invalidate IC */
|
/* Invalidate IC */
|
for (addr = 0; addr < 8192; addr += 16)
|
for (addr = 0; addr < 8192; addr += 16)
|
asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_ICBIR));
|
asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_ICBIR));
|
|
|
/* Enable IC */
|
/* Enable IC */
|
| Line 25... |
Line 26... |
|
|
int ic_disable_cmd (int argc, char *argv[])
|
int ic_disable_cmd (int argc, char *argv[])
|
{
|
{
|
unsigned long sr;
|
unsigned long sr;
|
|
|
if (argc) return -1;
|
if (argc)
|
|
return -1;
|
/* Disable IC */
|
/* Disable IC */
|
asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
|
asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
|
sr &= ~SPR_SR_ICE;
|
sr &= ~SPR_SR_ICE;
|
asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
|
asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
|
asm("l.nop");
|
asm("l.nop");
|
| Line 42... |
Line 44... |
int dc_enable_cmd (int argc, char *argv[])
|
int dc_enable_cmd (int argc, char *argv[])
|
{
|
{
|
unsigned long addr;
|
unsigned long addr;
|
unsigned long sr;
|
unsigned long sr;
|
|
|
if (argc) return -1;
|
if (argc)
|
|
return -1;
|
/* Invalidate DC */
|
/* Invalidate DC */
|
for (addr = 0; addr < 8192; addr += 16)
|
for (addr = 0; addr < 8192; addr += 16)
|
asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_DCBIR));
|
asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_DCBIR));
|
|
|
/* Enable DC */
|
/* Enable DC */
|
| Line 61... |
Line 64... |
}
|
}
|
|
|
int dc_disable_cmd (int argc, char *argv[])
|
int dc_disable_cmd (int argc, char *argv[])
|
{
|
{
|
|
|
if (argc) return -1;
|
if (argc)
|
|
return -1;
|
|
|
unsigned long sr = mfspr(SPR_SR);
|
unsigned long sr = mfspr(SPR_SR);
|
|
|
// If it's enabled and write back is on, we'd better flush it first
|
// If it's enabled and write back is on, we'd better flush it first
|
// (CWS=1 is write back)
|
// (CWS=1 is write back)
|
| Line 94... |
Line 98... |
if (argc == 1) {
|
if (argc == 1) {
|
addr = strtoul (argv[0], 0, 0);
|
addr = strtoul (argv[0], 0, 0);
|
/* Read SPR */
|
/* Read SPR */
|
asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
|
asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
|
printf ("\nSPR %04lx: %08lx", addr, val);
|
printf ("\nSPR %04lx: %08lx", addr, val);
|
} else return -1;
|
} else
|
|
return -1;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
int mtspr_cmd (int argc, char *argv[])
|
int mtspr_cmd (int argc, char *argv[])
|
{
|
{
|
| Line 108... |
Line 113... |
val = strtoul (argv[1], 0, 0);
|
val = strtoul (argv[1], 0, 0);
|
/* Write SPR */
|
/* Write SPR */
|
asm("l.mtspr %0,%1,0": : "r" (addr), "r" (val));
|
asm("l.mtspr %0,%1,0": : "r" (addr), "r" (val));
|
asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
|
asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
|
printf ("\nSPR %04lx: %08lx", addr, val);
|
printf ("\nSPR %04lx: %08lx", addr, val);
|
} else return -1;
|
} else
|
|
return -1;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
void module_cpu_init (void)
|
void module_cpu_init (void)
|
{
|
{
|
register_command ("ic_enable", "", "enable instruction cache", ic_enable_cmd);
|
register_command("ic_enable", "", "enable instruction cache",
|
register_command ("ic_disable", "", "disable instruction cache", ic_disable_cmd);
|
ic_enable_cmd);
|
|
register_command("ic_disable", "", "disable instruction cache",
|
|
ic_disable_cmd);
|
register_command ("dc_enable", "", "enable data cache", dc_enable_cmd);
|
register_command ("dc_enable", "", "enable data cache", dc_enable_cmd);
|
register_command ("dc_disable", "", "disable data cache", dc_disable_cmd);
|
register_command("dc_disable", "", "disable data cache",
|
|
dc_disable_cmd);
|
register_command ("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);
|
register_command ("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);
|
register_command ("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);
|
register_command ("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);
|
}
|
}
|
|
|
No newline at end of file
|
No newline at end of file
|
