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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [ram.ld] - Diff between revs 375 and 419

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Rev 375 Rev 419
Line 3... Line 3...
MEMORY
MEMORY
        {
        {
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
        /* Use all RAM */
        /* Use all RAM */
        /* Put all sections into ram */
        /* Put all sections into ram */
        /*
 
        ram     : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000
        ram     : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000
        */
 
        /* Uncomment the following to work around bad pages in a flash mem */
        /* Uncomment the following to work around bad pages in a flash mem */
        /* Put all sections except data, rodata into ram2 */
        /* Put all sections except data, rodata into ram2 */
        /* On ORSoC dev board devices, for pages 132-134 (256Byte pages) */
        /* On ORSoC dev board devices, for pages 132-134 (256Byte pages) */
 
        /*
        ram     : ORIGIN = 0x00001200, LENGTH = 0x8400 - 0x1200
        ram     : ORIGIN = 0x00001200, LENGTH = 0x8400 - 0x1200
        ram2     : ORIGIN = 0x8700, LENGTH = 0x02000000 - 0x8700
        ram2     : ORIGIN = 0x8700, LENGTH = 0x02000000 - 0x8700
 
        */
        /* Uncomment the following to work around bad pages in a flash mem */
        /* Uncomment the following to work around bad pages in a flash mem */
        /* Put all sections except data, rodata into ram2 */
        /* Put all sections except data, rodata into ram2 */
        /* On ORSoC dev board devices, for pages 180-182 (256Byte pages) */
        /* On ORSoC dev board devices, for pages 180-182 (256Byte pages) */
        /*
        /*
        ram     : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
        ram     : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
Line 37... Line 38...
        .text :
        .text :
        {
        {
        _text_begin = .;
        _text_begin = .;
        *(.text)
        *(.text)
        _text_end = .;
        _text_end = .;
        } > ram2
        } > ram
 
/*        } > ram2*/
 
 
        .data :
        .data :
/*      AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
/*      AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
        {
        {
        *(.data)
        *(.data)
Line 54... Line 56...
        } > ram
        } > ram
 
 
        .bss :
        .bss :
        {
        {
        *(.bss)
        *(.bss)
        } > ram2
        } > ram
 
/*        } > ram2 */
 
 
        .stack :
        .stack :
        {
        {
        *(.stack)
        *(.stack)
        _src_addr = .;
        _src_addr = .;
        } > ram2
        } > ram
 
/*        } > ram2 */
/*
/*
        .monitor :
        .monitor :
        {
        {
        *(.monitor)
        *(.monitor)
        } > ram
        } > ram

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