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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 140 |
Rev 175 |
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?rev2line? |
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/* Seen 3 bad pages, 180-182 (0xb400-0xb6ff), so put text after these pages */
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MEMORY
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{
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vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
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/*ram : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000*/
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ram : ORIGIN = 0x00001200, LENGTH = 0xB400 - 0x1200
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ram2 : ORIGIN = 0xb700, LENGTH = 0x02000000 - 0xb700
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/*flash : ORIGIN = 0xf0000000, LENGTH = 0x04000000*/
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}
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SECTIONS
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{
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.vectors :
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{
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*(.crc)
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*(.vectors)
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} > vectors
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.text :
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{
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_text_begin = .;
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*(.text)
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_text_end = .;
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} > ram2
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.data :
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/* AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/
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{
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*(.data)
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} > ram
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.rodata :
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{
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*(.rodata)
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*(.rodata.*)
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} > ram
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.bss :
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{
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*(.bss)
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} > ram
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.stack :
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{
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*(.stack)
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_src_addr = .;
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} > ram2
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/*
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.monitor :
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{
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*(.monitor)
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} > ram
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*/
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/*
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. += 0x100000;
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// This section was in cmds/load.c, but we don't need it -jb
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.config :
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{
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_cfg_start = .;
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*(.config)
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_cfg_end = .;
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} > ram
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*/
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/*
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. = 0xf0000100;
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.monitor ALIGN(0x40000) :
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{
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*(.monitor)
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} > flash
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. += 0x100000;
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.config ALIGN(0x40000) :
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{
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_cfg_start = .;
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*(.config)
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_cfg_end = .;
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} > flash
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*/
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}
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