URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 246 and 353

Rev 246	Rev 353
Line 318...	Line 318...
`l.ori r1,r1,lo(_stack-4)`	`l.ori r1,r1,lo(_stack-4)`
`l.addi r2,r0,-3`	`l.addi r2,r0,-3`
`l.and r1,r1,r2`	`l.and r1,r1,r2`
`/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/`	`/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/`

`l.movhi r3,hi(main)`	`l.movhi r3,hi(_main)`
`l.ori r3,r3,lo(main)`	`l.ori r3,r3,lo(_main)`
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`


`_tick:`	`_tick:`
Line 355...	Line 355...
`l.sw 0x68(r1), r28`	`l.sw 0x68(r1), r28`
`l.sw 0x6c(r1), r29`	`l.sw 0x6c(r1), r29`
`l.sw 0x70(r1), r30`	`l.sw 0x70(r1), r30`
`l.sw 0x74(r1), r31`	`l.sw 0x74(r1), r31`

`l.movhi r3,hi(tick_interrupt)`	`l.movhi r3,hi(_tick_interrupt)`
`l.ori r3,r3,lo(tick_interrupt)`	`l.ori r3,r3,lo(_tick_interrupt)`
`l.jalr r3`	`l.jalr r3`
`l.nop`	`l.nop`

`l.lwz r3,0x4(r1)`	`l.lwz r3,0x4(r1)`
`l.lwz r4,0x8(r1)`	`l.lwz r4,0x8(r1)`
Line 426...	Line 426...
`l.sw 0x68(r1), r28`	`l.sw 0x68(r1), r28`
`l.sw 0x6c(r1), r29`	`l.sw 0x6c(r1), r29`
`l.sw 0x70(r1), r30`	`l.sw 0x70(r1), r30`
`l.sw 0x74(r1), r31`	`l.sw 0x74(r1), r31`

`l.movhi r3,hi(int_main)`	`l.movhi r3,hi(_int_main)`
`l.ori r3,r3,lo(int_main)`	`l.ori r3,r3,lo(_int_main)`
`l.jalr r3`	`l.jalr r3`
`l.nop`	`l.nop`

`l.lwz r3,0x4(r1)`	`l.lwz r3,0x4(r1)`
`l.lwz r4,0x8(r1)`	`l.lwz r4,0x8(r1)`