| Line 1... |
Line 1... |
#include "spr-defs.h"
|
#include "spr-defs.h"
|
#include "board.h"
|
#include "board.h"
|
#include "mc.h"
|
|
|
#define TRAP_ON_ERROR 0
|
|
#define LOOP_ON_ERROR 0
|
|
#define EXIT_NOP_ON_ERROR 1
|
|
#define PRINT_AND_RESET_ON_ERROR 1
|
|
|
.extern _src_beg
|
.extern _src_beg
|
.extern _dst_beg
|
.extern _dst_beg
|
.extern _dst_end
|
.extern _dst_end
|
.extern int_main
|
.extern int_main
|
.extern int_error
|
.extern int_error
|
.extern tick_interrupt
|
.extern tick_interrupt
|
.extern _crc32
|
.extern _crc32
|
|
|
.global _align
|
|
.global _calc_mycrc32
|
.global _calc_mycrc32
|
.global _mycrc32
|
.global _mycrc32
|
.global _mysize
|
.global _mysize
|
|
|
.section .stack, "aw", @nobits
|
.section .stack, "aw", @nobits
|
| Line 56... |
Line 59... |
.else
|
.else
|
.section .vectors, "ax"
|
.section .vectors, "ax"
|
.endif
|
.endif
|
|
|
_reset:
|
_reset:
|
.if IN_FLASH
|
|
l.movhi r3,hi(MC_BASE_ADDR)
|
|
l.ori r3,r3,MC_BA_MASK
|
|
l.addi r5,r0,0x00
|
|
l.sw 0(r3),r5
|
|
.endif
|
|
l.movhi r0, 0
|
l.movhi r0, 0
|
/* Clear status register, set supervisor mode */
|
/* Clear status register, set supervisor mode */
|
l.ori r1, r0, SPR_SR_SM
|
l.ori r1, r0, SPR_SR_SM
|
l.mtspr r0, r1, SPR_SR
|
l.mtspr r0, r1, SPR_SR
|
/* Clear timer */
|
/* Clear timer */
|
| Line 81... |
Line 78... |
.org 0x200
|
.org 0x200
|
.else
|
.else
|
.org (0x200 - 0x100 + _reset)
|
.org (0x200 - 0x100 + _reset)
|
.endif
|
.endif
|
_buserr:
|
_buserr:
|
.if 0
|
.if TRAP_ON_ERROR
|
/* Just trap */
|
/* Just trap */
|
l.trap 0
|
l.trap 0
|
.endif
|
.endif
|
.if 0
|
.if EXIT_NOP_ON_ERROR
|
l.nop 0x1
|
l.nop 0x1
|
|
.endif
|
|
.if LOOP_ON_ERROR
|
l.j 0
|
l.j 0
|
l.nop
|
l.nop
|
.endif
|
.endif
|
l.j _int_error
|
.if PRINT_AND_RESET_ON_ERROR
|
|
l.mfspr r4, r0, SPR_EPCR_BASE
|
|
l.j _int_error /* This will reset */
|
l.ori r3, r0, 0x2
|
l.ori r3, r0, 0x2
|
|
.endif
|
.if IN_FLASH
|
.if IN_FLASH
|
.section .vectors, "ax"
|
.section .vectors, "ax"
|
.org 0x500
|
.org 0x500
|
.else
|
.else
|
.org (0x500 - 0x100 + _reset)
|
.org (0x500 - 0x100 + _reset)
|
.endif
|
.endif
|
_tickint:
|
_tickint:
|
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
|
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
|
/* Simply load timer_ticks variable and increment */
|
/* Simply load timer_ticks variable and increment */
|
.extern _timer_ticks
|
.extern _timer_ticks
|
l.addi r1, r1, -8
|
l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/
|
l.sw 0(r1), r25
|
l.sw 0(r1), r25
|
l.sw 4(r1), r26
|
l.sw 4(r1), r26
|
l.movhi r25, hi(timestamp)
|
l.movhi r25, hi(timestamp)
|
l.ori r25, r25, lo(timestamp)
|
l.ori r25, r25, lo(timestamp)
|
l.lwz r26, 0(r25) /* Load variable addr.*/
|
l.lwz r26, 0(r25) /* Load variable addr.*/
|
| Line 116... |
Line 117... |
l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */
|
l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */
|
l.ori r25, r25, lo(TIMER_RELOAD_VALUE)
|
l.ori r25, r25, lo(TIMER_RELOAD_VALUE)
|
l.mtspr r0, r25, SPR_TTMR /* Reset timer */
|
l.mtspr r0, r25, SPR_TTMR /* Reset timer */
|
l.lwz r25, 0(r1)
|
l.lwz r25, 0(r1)
|
l.lwz r26, 4(r1)
|
l.lwz r26, 4(r1)
|
l.addi r1, r1, 8
|
l.addi r1, r1, 136
|
l.rfe
|
l.rfe
|
|
|
.if IN_FLASH
|
.if IN_FLASH
|
.section .vectors, "ax"
|
.section .vectors, "ax"
|
.org 0x600
|
.org 0x600
|
.else
|
.else
|
.org (0x600 - 0x100 + _reset)
|
.org (0x600 - 0x100 + _reset)
|
.endif
|
.endif
|
_alignerr:
|
_alignerr:
|
.if 0
|
.if TRAP_ON_ERROR
|
|
/* Just trap */
|
l.trap 0
|
l.trap 0
|
.endif
|
.endif
|
.if 0
|
.if EXIT_NOP_ON_ERROR
|
l.nop 0x1
|
l.nop 0x1
|
|
.endif
|
|
.if LOOP_ON_ERROR
|
l.j 0
|
l.j 0
|
l.nop
|
l.nop
|
.endif
|
.endif
|
l.j _int_error
|
.if PRINT_AND_RESET_ON_ERROR
|
|
l.mfspr r4, r0, SPR_EPCR_BASE
|
|
l.j _int_error /* This will reset */
|
l.ori r3, r0, 0x6
|
l.ori r3, r0, 0x6
|
|
.endif
|
|
|
.if IN_FLASH
|
.if IN_FLASH
|
.org 0x700
|
.org 0x700
|
.else
|
.else
|
.org (0x700 - 0x100 + _reset)
|
.org (0x700 - 0x100 + _reset)
|
.endif
|
.endif
|
_illinsn:
|
_illinsn:
|
.if 0
|
.if TRAP_ON_ERROR
|
/* Just trap */
|
/* Just trap */
|
l.trap 0
|
l.trap 0
|
.endif
|
.endif
|
.if 0
|
.if EXIT_NOP_ON_ERROR
|
l.nop 0x1
|
l.nop 0x1
|
|
.endif
|
|
.if LOOP_ON_ERROR
|
l.j 0
|
l.j 0
|
l.nop
|
l.nop
|
.endif
|
.endif
|
l.j _int_error
|
.if PRINT_AND_RESET_ON_ERROR
|
|
l.mfspr r4, r0, SPR_EPCR_BASE
|
|
l.j _int_error /* This will reset */
|
l.ori r3, r0, 0x7
|
l.ori r3, r0, 0x7
|
|
.endif
|
.if IN_FLASH
|
.if IN_FLASH
|
.org 0x800
|
.org 0x800
|
.else
|
.else
|
.org (0x800 - 0x100 + _reset)
|
.org (0x800 - 0x100 + _reset)
|
.endif
|
.endif
|
_userint:
|
_userint:
|
l.addi r1,r1,-128
|
l.addi r1,r1,-256 /*(128 + 128) */
|
l.sw 0x0(r1),r2
|
l.sw 0x0(r1),r2
|
l.addi r2, r1, 128
|
l.addi r2, r1, 256
|
l.sw 0x4(r1), r3
|
l.sw 0x4(r1), r3
|
l.movhi r3,hi(_int_wrapper)
|
l.movhi r3,hi(_int_wrapper)
|
l.ori r3,r3,lo(_int_wrapper)
|
l.ori r3,r3,lo(_int_wrapper)
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
|
|
.section .text
|
.section .text
|
_start:
|
_start:
|
.if IN_FLASH
|
|
/* l.jal _init_mc
|
|
l.nop
|
|
*/
|
|
/* Wait for SDRAM */
|
|
l.addi r3,r0,0x1000
|
|
1: l.sfeqi r3,0
|
|
l.bnf 1b
|
|
l.addi r3,r3,-1
|
|
.endif
|
|
/* Copy form flash to sram */
|
/* Copy form flash to sram */
|
.if IN_FLASH
|
.if IN_FLASH
|
l.movhi r3,hi(_src_beg)
|
l.movhi r3,hi(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.ori r3,r3,lo(_src_beg)
|
l.movhi r4,hi(_vec_start)
|
l.movhi r4,hi(_vec_start)
|
| Line 331... |
Line 332... |
/* Set up stack */
|
/* Set up stack */
|
l.movhi r1,hi(_stack-4)
|
l.movhi r1,hi(_stack-4)
|
l.ori r1,r1,lo(_stack-4)
|
l.ori r1,r1,lo(_stack-4)
|
l.addi r2,r0,-3
|
l.addi r2,r0,-3
|
l.and r1,r1,r2
|
l.and r1,r1,r2
|
/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/
|
|
|
|
l.movhi r3,hi(main)
|
l.movhi r3,hi(main)
|
l.ori r3,r3,lo(main)
|
l.ori r3,r3,lo(main)
|
l.jr r3
|
l.jr r3
|
l.nop
|
l.nop
|
| Line 405... |
Line 405... |
l.lwz r29,0x6c(r1)
|
l.lwz r29,0x6c(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r30,0x70(r1)
|
l.lwz r31,0x74(r1)
|
l.lwz r31,0x74(r1)
|
|
|
l.lwz r2, 0x0(r1)
|
l.lwz r2, 0x0(r1)
|
l.addi r1,r1,128
|
l.addi r1,r1,256
|
l.rfe
|
l.rfe
|
l.nop
|
l.nop
|
|
|
|
|
_align:
|
|
l.sw 0x0c(r1),r3
|
|
l.sw 0x10(r1),r4
|
|
l.sw 0x14(r1),r5
|
|
l.sw 0x18(r1),r6
|
|
l.sw 0x1c(r1),r7
|
|
l.sw 0x20(r1),r8
|
|
l.sw 0x24(r1),r9
|
|
l.sw 0x28(r1),r10
|
|
l.sw 0x2c(r1),r11
|
|
l.sw 0x30(r1),r12
|
|
l.sw 0x34(r1),r13
|
|
l.sw 0x38(r1),r14
|
|
l.sw 0x3c(r1),r15
|
|
l.sw 0x40(r1),r16
|
|
l.sw 0x44(r1),r17
|
|
l.sw 0x48(r1),r18
|
|
l.sw 0x4c(r1),r19
|
|
l.sw 0x50(r1),r20
|
|
l.sw 0x54(r1),r21
|
|
l.sw 0x58(r1),r22
|
|
l.sw 0x5c(r1),r23
|
|
l.sw 0x60(r1),r24
|
|
l.sw 0x64(r1),r25
|
|
l.sw 0x68(r1),r26
|
|
l.sw 0x6c(r1),r27
|
|
l.sw 0x70(r1),r28
|
|
l.sw 0x74(r1),r29
|
|
l.sw 0x78(r1),r30
|
|
l.sw 0x7c(r1),r31
|
|
|
|
l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
|
|
l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
|
|
|
|
l.lwz r3,0(r5) /* Load insn */
|
|
l.srli r4,r3,26 /* Shift left to get the insn opcode */
|
|
|
|
l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
|
|
l.bf jmp
|
|
l.sfeqi r4,0x01
|
|
l.bf jmp
|
|
l.sfeqi r4,0x03
|
|
l.bf jmp
|
|
l.sfeqi r4,0x04
|
|
l.bf jmp
|
|
l.sfeqi r4,0x11
|
|
l.bf jr
|
|
l.sfeqi r4,0x12
|
|
l.bf jr
|
|
l.nop
|
|
l.j 1f
|
|
l.addi r5,r5,4 /* Increment PC to get return insn address */
|
|
|
|
jmp:
|
|
l.slli r4,r3,6 /* Get the signed extended jump length */
|
|
l.srai r4,r4,4
|
|
|
|
l.lwz r3,4(r5) /* Load the real load/store insn */
|
|
|
|
l.add r5,r5,r4 /* Calculate jump target address */
|
|
|
|
l.j 1f
|
|
l.srli r4,r3,26 /* Shift left to get the insn opcode */
|
|
|
|
jr:
|
|
l.slli r4,r3,9 /* Shift to get the reg nb */
|
|
l.andi r4,r4,0x7c
|
|
|
|
l.lwz r3,4(r5) /* Load the real load/store insn */
|
|
|
|
l.add r4,r4,r1 /* Load the jump register value from the stack */
|
|
l.lwz r5,0(r4)
|
|
|
|
l.srli r4,r3,26 /* Shift left to get the insn opcode */
|
|
|
|
|
|
1: l.mtspr r0,r5,SPR_EPCR_BASE
|
|
|
|
l.sfeqi r4,0x26
|
|
l.bf lhs
|
|
l.sfeqi r4,0x25
|
|
l.bf lhz
|
|
l.sfeqi r4,0x22
|
|
l.bf lws
|
|
l.sfeqi r4,0x21
|
|
l.bf lwz
|
|
l.sfeqi r4,0x37
|
|
l.bf sh
|
|
l.sfeqi r4,0x35
|
|
l.bf sw
|
|
l.nop
|
|
|
|
1: l.j 1b /* I don't know what to do */
|
|
l.nop
|
|
|
|
lhs: l.lbs r5,0(r2)
|
|
l.slli r5,r5,8
|
|
l.lbz r6,1(r2)
|
|
l.or r5,r5,r6
|
|
l.srli r4,r3,19
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.j align_end
|
|
l.sw 0(r4),r5
|
|
|
|
lhz: l.lbz r5,0(r2)
|
|
l.slli r5,r5,8
|
|
l.lbz r6,1(r2)
|
|
l.or r5,r5,r6
|
|
l.srli r4,r3,19
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.j align_end
|
|
l.sw 0(r4),r5
|
|
|
|
lws: l.lbs r5,0(r2)
|
|
l.slli r5,r5,24
|
|
l.lbz r6,1(r2)
|
|
l.slli r6,r6,16
|
|
l.or r5,r5,r6
|
|
l.lbz r6,2(r2)
|
|
l.slli r6,r6,8
|
|
l.or r5,r5,r6
|
|
l.lbz r6,3(r2)
|
|
l.or r5,r5,r6
|
|
l.srli r4,r3,19
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.j align_end
|
|
l.sw 0(r4),r5
|
|
|
|
lwz: l.lbz r5,0(r2)
|
|
l.slli r5,r5,24
|
|
l.lbz r6,1(r2)
|
|
l.slli r6,r6,16
|
|
l.or r5,r5,r6
|
|
l.lbz r6,2(r2)
|
|
l.slli r6,r6,8
|
|
l.or r5,r5,r6
|
|
l.lbz r6,3(r2)
|
|
l.or r5,r5,r6
|
|
l.srli r4,r3,19
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.j align_end
|
|
l.sw 0(r4),r5
|
|
|
|
sh:
|
|
l.srli r4,r3,9
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.lwz r5,0(r4)
|
|
l.sb 1(r2),r5
|
|
l.srli r5,r5,8
|
|
l.j align_end
|
|
l.sb 0(r2),r5
|
|
|
|
sw:
|
|
l.srli r4,r3,9
|
|
l.andi r4,r4,0x7c
|
|
l.add r4,r4,r1
|
|
l.lwz r5,0(r4)
|
|
l.sb 3(r2),r5
|
|
l.srli r5,r5,8
|
|
l.sb 2(r2),r5
|
|
l.srli r5,r5,8
|
|
l.sb 1(r2),r5
|
|
l.srli r5,r5,8
|
|
l.j align_end
|
|
l.sb 0(r2),r5
|
|
|
|
align_end:
|
|
l.lwz r2,0x08(r1)
|
|
l.lwz r3,0x0c(r1)
|
|
l.lwz r4,0x10(r1)
|
|
l.lwz r5,0x14(r1)
|
|
l.lwz r6,0x18(r1)
|
|
l.lwz r7,0x1c(r1)
|
|
l.lwz r8,0x20(r1)
|
|
l.lwz r9,0x24(r1)
|
|
l.lwz r10,0x28(r1)
|
|
l.lwz r11,0x2c(r1)
|
|
l.lwz r12,0x30(r1)
|
|
l.lwz r13,0x34(r1)
|
|
l.lwz r14,0x38(r1)
|
|
l.lwz r15,0x3c(r1)
|
|
l.lwz r16,0x40(r1)
|
|
l.lwz r17,0x44(r1)
|
|
l.lwz r18,0x48(r1)
|
|
l.lwz r19,0x4c(r1)
|
|
l.lwz r20,0x50(r1)
|
|
l.lwz r21,0x54(r1)
|
|
l.lwz r22,0x58(r1)
|
|
l.lwz r23,0x5c(r1)
|
|
l.lwz r24,0x60(r1)
|
|
l.lwz r25,0x64(r1)
|
|
l.lwz r26,0x68(r1)
|
|
l.lwz r27,0x6c(r1)
|
|
l.lwz r28,0x70(r1)
|
|
l.lwz r29,0x74(r1)
|
|
l.lwz r30,0x78(r1)
|
|
l.mfspr r31,r0,0x40
|
|
l.lwz r31,0x7c(r1)
|
|
l.addi r1,r1,128
|
|
l.rfe
|
|
|
|
|
|
/* Jump to error function. Clobber r2 */
|
/* Jump to error function. Clobber r2 */
|
_int_error:
|
_int_error:
|
l.movhi r2,hi(int_error)
|
l.movhi r2,hi(int_error)
|
l.ori r2,r2,lo(int_error)
|
l.ori r2,r2,lo(int_error)
|
l.jr r2
|
l.jr r2
|
