OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 463 and 467

Show entire file | Details | Blame | View Log

Rev 463 Rev 467
Line 4... Line 4...
#define TRAP_ON_ERROR 0
#define TRAP_ON_ERROR 0
#define LOOP_ON_ERROR 0
#define LOOP_ON_ERROR 0
#define EXIT_NOP_ON_ERROR 1
#define EXIT_NOP_ON_ERROR 1
#define PRINT_AND_RESET_ON_ERROR 1
#define PRINT_AND_RESET_ON_ERROR 1
 
 
        .extern _src_beg
 
        .extern _dst_beg
 
        .extern _dst_end
 
        .extern int_main
        .extern int_main
        .extern int_error
        .extern int_error
        .extern tick_interrupt
 
        .extern _crc32
 
        .extern _bstart
        .extern _bstart
        .extern _bend
        .extern _bend
        .global _calc_mycrc32
 
        .global _mycrc32
 
        .global _mysize
 
 
 
        .section .stack, "aw", @nobits
        .section .stack, "aw", @nobits
.space  STACK_SIZE
.space  STACK_SIZE
_stack:
_stack:
        .section .crc
 
_mycrc32:
 
        .word   0xcccccccc
 
_mysize:
 
        .word 0xdddddddd
 
 
 
.if SELF_CHECK
 
_calc_mycrc32:
 
        l.addi  r3,r0,0
 
        l.movhi r4,hi(_calc_mycrc32)
 
        l.ori   r4,r4,lo(_calc_mycrc32)
 
        l.movhi r5,hi(_mysize)
 
        l.ori   r5,r5,lo(_mysize)
 
        l.lwz   r5,0(r5)
 
        l.addi  r1,r1,-4
 
        l.sw    0(r1),r9
 
 
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
 
        l.jal           _crc32
 
        l.nop
 
 
 
        l.movhi r3,hi(_mycrc32)
 
        l.ori   r3,r3,lo(_mycrc32)
 
        l.lwz   r3,0(r3)
 
 
 
        l.xor     r11,r3,r11
 
        l.lwz   r9,0(r1)
 
        l.jr    r9
 
        l.addi  r1,r1,4
 
.endif
 
 
 
        .org 0x100
 
 
 
        .section .vectors, "ax"
        .section .vectors, "ax"
 
 
 
        .org 0x100
_reset:
_reset:
        l.movhi r0, 0
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        l.mtspr r0, r1, SPR_SR
Line 272... Line 234...
        /* Set up stack */
        /* Set up stack */
        l.movhi r1,hi(_stack-4)
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
        l.and   r1,r1,r2
 
        l.or    r2,r1,r1
 
 
        /* Clear BSS */
        /* Clear BSS */
        l.movhi r3, hi(_bstart)
        l.movhi r3, hi(_bstart)
        l.ori   r3, r3, lo(_bstart)
        l.ori   r3, r3, lo(_bstart)
        l.movhi r4, hi(_bend)
        l.movhi r4, hi(_bend)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.