URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 175 and 246

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Rev 175	Rev 246
Line 1...	Line 1...
`#include "spr_defs.h"`	`#include "spr-defs.h"`
`#include "board.h"`	`#include "board.h"`
`#include "mc.h"`	`#include "mc.h"`

`.extern _reset_support`	`.extern _reset_support`
`.extern _eth_int`	`.extern _eth_int`
Line 67...	Line 67...
`l.movhi r3,hi(MC_BASE_ADDR)`	`l.movhi r3,hi(MC_BASE_ADDR)`
`l.ori r3,r3,MC_BA_MASK`	`l.ori r3,r3,MC_BA_MASK`
`l.addi r5,r0,0x00`	`l.addi r5,r0,0x00`
`l.sw 0(r3),r5`	`l.sw 0(r3),r5`
`.endif`	`.endif`
`l.addi r3,r0,SPR_SR_SM`	`l.movhi r0, 0`
`l.mtspr r0,r3,SPR_SR`	`/* Clear status register, set supervisor mode */`
	`l.ori r1, r0, SPR_SR_SM`
	`l.mtspr r0, r1, SPR_SR`
	`/* Clear timer */`
	`l.mtspr r0, r0, SPR_TTMR`
	`/* Jump to start routine */`
`l.movhi r3,hi(_start)`	`l.movhi r3,hi(_start)`
`l.ori r3,r3,lo(_start)`	`l.ori r3,r3,lo(_start)`
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`

Line 81...	Line 86...
`.org 0x200`	`.org 0x200`
`.else`	`.else`
`.org (0x200 - 0x100 + _reset)`	`.org (0x200 - 0x100 + _reset)`
`.endif`	`.endif`
`_buserr:`	`_buserr:`
	`.if 0`
`/* Just trap */`	`/* Just trap */`
`l.trap 0`	`l.trap 0`
`l.nop`	`.endif`
	`l.nop 0x1`
`l.j 0`	`l.j 0`
`l.nop`	`l.nop`


`.if IN_FLASH`	`.if IN_FLASH`
Line 96...	Line 103...
`.else`	`.else`
`.org (0x500 - 0x100 + _reset)`	`.org (0x500 - 0x100 + _reset)`
`.endif`	`.endif`
`_tickint:`	`_tickint:`
`l.addi r1,r1,-128`	`l.addi r1,r1,-128`
`l.sw 0x4(r1),r2`	`l.sw 0(r1), r2`
`l.movhi r2,hi(_tick)`	`l.addi r2, r1, 128`
`l.ori r2,r2,lo(_tick)`	`l.sw 0x4(r1),r3`
`l.jr r2`	`l.movhi r3,hi(_tick)`
	`l.ori r3,r3,lo(_tick)`
	`l.jr r3`
`l.nop`	`l.nop`

`.if IN_FLASH`	`.if IN_FLASH`
`.section .vectors, "ax"`	`.section .vectors, "ax"`
`.org 0x600`	`.org 0x600`
`.else`	`.else`
`.org (0x600 - 0x100 + _reset)`	`.org (0x600 - 0x100 + _reset)`
`.endif`	`.endif`
`_alignerr:`	`_alignerr:`
`.if 0`	`.if 0`
`/* Let's crash on align errors */`
`l.addi r1,r1,-128`
`l.sw 0x08(r1),r2`
`l.movhi r2,hi(_align)`
`l.ori r2,r2,lo(_align)`
`l.jr r2`
`l.nop`
`.endif`
`l.trap 0`	`l.trap 0`
`l.nop`	`.endif`
	`l.nop 0x1`
`l.j 0`	`l.j 0`
`l.nop`	`l.nop`

`.if IN_FLASH`	`.if IN_FLASH`
`.org 0x700`	`.org 0x700`
`.else`	`.else`
`.org (0x700 - 0x100 + _reset)`	`.org (0x700 - 0x100 + _reset)`
`.endif`	`.endif`
`_illinsn:`	`_illinsn:`
	`.if 0`
`/* Just trap */`	`/* Just trap */`
`l.trap 0`	`l.trap 0`
`l.nop`	`.endif`
	`l.nop 0x1`
`l.j 0`	`l.j 0`
`l.nop`	`l.nop`


`.if IN_FLASH`	`.if IN_FLASH`
Line 143...	Line 147...
`.else`	`.else`
`.org (0x800 - 0x100 + _reset)`	`.org (0x800 - 0x100 + _reset)`
`.endif`	`.endif`
`_userint:`	`_userint:`
`l.addi r1,r1,-128`	`l.addi r1,r1,-128`
`l.sw 0x4(r1),r2`	`l.sw 0x0(r1),r2`
`l.movhi r2,hi(_int_wrapper)`	`l.addi r2, r1, 128`
`l.ori r2,r2,lo(_int_wrapper)`	`l.sw 0x4(r1), r3`
`l.jr r2`	`l.movhi r3,hi(_int_wrapper)`
	`l.ori r3,r3,lo(_int_wrapper)`
	`l.jr r3`
`l.nop`	`l.nop`

`.section .text`	`.section .text`
`_start:`	`_start:`
`.if IN_FLASH`	`.if IN_FLASH`
Line 199...	Line 205...
`1:`	`1:`
`l.addi r3,r0,0`	`l.addi r3,r0,0`
`l.addi r4,r0,0`	`l.addi r4,r0,0`
`3:`	`3:`
`.endif`	`.endif`
`/*`
`l.jal _ic_disable`
`l.nop`
`*/`
`.if IC_ENABLE`
`l.jal _ic_enable`
`l.nop`
`.endif`

`.if DC_ENABLE`
`l.jal _dc_enable`
`l.nop`
`.endif`

`l.movhi r1,hi(_stack-4)`
`l.ori r1,r1,lo(_stack-4)`
`l.addi r2,r0,-3`
`l.and r1,r1,r2`

`l.movhi r2,hi(_main)`	`/* Instruction cache enable */`
`l.ori r2,r2,lo(_main)`	`/* Check if IC present and skip enabling otherwise */`
`l.jr r2`	`l.mfspr r24,r0,SPR_UPR`
`l.addi r2,r0,0`	`l.andi r26,r24,SPR_UPR_ICP`
	`l.sfeq r26,r0`
`_ic_enable:`	`l.bf .L8`
	`l.nop`
`/* Flush IC */`
`l.addi r10,r0,0`	`/* Disable IC */`
`l.addi r11,r0,IC_SIZE`	`l.mfspr r6,r0,SPR_SR`
`1:`	`l.addi r5,r0,-1`
`l.mtspr r0,r10,SPR_ICBIR`	`l.xori r5,r5,SPR_SR_ICE`
`l.sfne r10,r11`	`l.and r5,r6,r5`
`l.bf 1b`	`l.mtspr r0,r5,SPR_SR`
`l.addi r10,r10,16`
	`/* Establish cache block size`
	`If BS=0, 16;`
	`If BS=1, 32;`
	`r14 contain block size`
	`*/`
	`l.mfspr r24,r0,SPR_ICCFGR`
	`l.andi r26,r24,SPR_ICCFGR_CBS`
	`l.srli r28,r26,7`
	`l.ori r30,r0,16`
	`l.sll r14,r30,r28`

	`/* Establish number of cache sets`
	`r16 contains number of cache sets`
	`r28 contains log(# of cache sets)`
	`*/`
	`l.andi r26,r24,SPR_ICCFGR_NCS`
	`l.srli r28,r26,3`
	`l.ori r30,r0,1`
	`l.sll r16,r30,r28`

	`/* Invalidate IC */`
	`l.addi r6,r0,0`
	`l.sll r5,r14,r28`

	`.L7:`
	`l.mtspr r0,r6,SPR_ICBIR`
	`l.sfne r6,r5`
	`l.bf .L7`
	`l.add r6,r6,r14`

`/* Enable IC */`	`/* Enable IC */`
`l.mfspr r10,r0,SPR_SR`	`l.mfspr r6,r0,SPR_SR`
`l.ori r10,r10,(SPR_SR_ICE\|SPR_SR_SM)`	`l.ori r6,r6,SPR_SR_ICE`
`l.mtspr r0,r10,SPR_SR`	`l.mtspr r0,r6,SPR_SR`
`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

`l.jr r9`
`l.nop`

`_ic_disable:`

`l.addi r10,r0,0`
`l.addi r11,r0,IC_SIZE`
`1:`
`l.mtspr r0,r10,SPR_ICBIR`
`l.sfne r10,r11`
`l.bf 1b`
`l.addi r10,r10,16`


`l.mfspr r10,r0,SPR_SR`
`l.movhi r11, 0xffff`
`l.ori r11, r11, 0xffef`
`l.and r10, r10, r11`
`l.ori r10, r10, SPR_SR_SM`
`l.mtspr r0,r10,SPR_SR`
`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`
`l.nop`	`l.nop`

`l.jr r9`	`.L8:`
	`/* Data cache enable */`
	`/* Check if DC present and skip enabling otherwise */`
	`l.mfspr r24,r0,SPR_UPR`
	`l.andi r26,r24,SPR_UPR_DCP`
	`l.sfeq r26,r0`
	`l.bf .L10`
`l.nop`	`l.nop`
	`/* Disable DC */`
`_dc_enable:`	`l.mfspr r6,r0,SPR_SR`
	`l.addi r5,r0,-1`
`/* Flush DC */`	`l.xori r5,r5,SPR_SR_DCE`
`l.addi r10,r0,0`	`l.and r5,r6,r5`
`l.addi r11,r0,DC_SIZE`	`l.mtspr r0,r5,SPR_SR`
`1:`	`/* Establish cache block size`
`l.mtspr r0,r10,SPR_DCBIR`	`If BS=0, 16;`
`l.sfne r10,r11`	`If BS=1, 32;`
`l.bf 1b`	`r14 contain block size`
`l.addi r10,r10,16`	`*/`
	`l.mfspr r24,r0,SPR_DCCFGR`
	`l.andi r26,r24,SPR_DCCFGR_CBS`
	`l.srli r28,r26,7`
	`l.ori r30,r0,16`
	`l.sll r14,r30,r28`
	`/* Establish number of cache sets`
	`r16 contains number of cache sets`
	`r28 contains log(# of cache sets)`
	`*/`
	`l.andi r26,r24,SPR_DCCFGR_NCS`
	`l.srli r28,r26,3`
	`l.ori r30,r0,1`
	`l.sll r16,r30,r28`
	`/* Invalidate DC */`
	`l.addi r6,r0,0`
	`l.sll r5,r14,r28`
	`.L9:`
	`l.mtspr r0,r6,SPR_DCBIR`
	`l.sfne r6,r5`
	`l.bf .L9`
	`l.add r6,r6,r14`
`/* Enable DC */`	`/* Enable DC */`
`l.mfspr r10,r0,SPR_SR`	`l.mfspr r6,r0,SPR_SR`
`l.ori r10,r10,(SPR_SR_DCE\|SPR_SR_SM)`	`l.ori r6,r6,SPR_SR_DCE`
`l.mtspr r0,r10,SPR_SR`	`l.mtspr r0,r6,SPR_SR`

`l.jr r9`	`.L10:`
	`/* Set up stack */`
	`l.movhi r1,hi(_stack-4)`
	`l.ori r1,r1,lo(_stack-4)`
	`l.addi r2,r0,-3`
	`l.and r1,r1,r2`
	`/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/`

	`l.movhi r3,hi(main)`
	`l.ori r3,r3,lo(main)`
	`l.jr r3`
`l.nop`	`l.nop`


`_tick:`	`_tick:`

`l.sw 0x8(r1),r4`	`l.sw 0x8(r1),r4`
`l.sw 0xc(r1),r5`	`l.sw 0xc(r1),r5`
`l.sw 0x10(r1),r6`	`l.sw 0x10(r1),r6`
`l.sw 0x14(r1),r7`	`l.sw 0x14(r1),r7`
`l.sw 0x18(r1),r8`	`l.sw 0x18(r1),r8`
Line 322...	Line 354...
`l.sw 0x64(r1),r27`	`l.sw 0x64(r1),r27`
`l.sw 0x68(r1),r28`	`l.sw 0x68(r1),r28`
`l.sw 0x6c(r1),r29`	`l.sw 0x6c(r1),r29`
`l.sw 0x70(r1),r30`	`l.sw 0x70(r1),r30`
`l.sw 0x74(r1),r31`	`l.sw 0x74(r1),r31`
`l.sw 0x78(r1),r3`

`l.movhi r3,hi(_tick_interrupt)`	`l.movhi r3,hi(tick_interrupt)`
`l.ori r3,r3,lo(_tick_interrupt)`	`l.ori r3,r3,lo(tick_interrupt)`
`l.jalr r3`	`l.jalr r3`
`l.nop`	`l.nop`

`l.lwz r2,0x4(r1)`	`l.lwz r3,0x4(r1)`
`l.lwz r4,0x8(r1)`	`l.lwz r4,0x8(r1)`
`l.lwz r5,0xc(r1)`	`l.lwz r5,0xc(r1)`
`l.lwz r6,0x10(r1)`	`l.lwz r6,0x10(r1)`
`l.lwz r7,0x14(r1)`	`l.lwz r7,0x14(r1)`
`l.lwz r8,0x18(r1)`	`l.lwz r8,0x18(r1)`
Line 357...	Line 388...
`l.lwz r26,0x60(r1)`	`l.lwz r26,0x60(r1)`
`l.lwz r27,0x64(r1)`	`l.lwz r27,0x64(r1)`
`l.lwz r28,0x68(r1)`	`l.lwz r28,0x68(r1)`
`l.lwz r29,0x6c(r1)`	`l.lwz r29,0x6c(r1)`
`l.lwz r30,0x70(r1)`	`l.lwz r30,0x70(r1)`
`l.mfspr r31,r0,0x40`
`l.lwz r31,0x74(r1)`	`l.lwz r31,0x74(r1)`
`l.lwz r3,0x78(r1)`

	`l.lwz r2, 0x0(r1)`
`l.addi r1,r1,128`	`l.addi r1,r1,128`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`

`_int_wrapper:`	`_int_wrapper:`

`l.sw 0x8(r1),r4`	`l.sw 0x8(r1),r4`
`l.sw 0xc(r1),r5`	`l.sw 0xc(r1),r5`
`l.sw 0x10(r1),r6`	`l.sw 0x10(r1),r6`
`l.sw 0x14(r1),r7`	`l.sw 0x14(r1),r7`
`l.sw 0x18(r1),r8`	`l.sw 0x18(r1),r8`
Line 394...	Line 425...
`l.sw 0x64(r1),r27`	`l.sw 0x64(r1),r27`
`l.sw 0x68(r1),r28`	`l.sw 0x68(r1),r28`
`l.sw 0x6c(r1),r29`	`l.sw 0x6c(r1),r29`
`l.sw 0x70(r1),r30`	`l.sw 0x70(r1),r30`
`l.sw 0x74(r1),r31`	`l.sw 0x74(r1),r31`
`l.sw 0x78(r1),r3`

`l.movhi r3,hi(_int_main)`	`l.movhi r3,hi(int_main)`
`l.ori r3,r3,lo(_int_main)`	`l.ori r3,r3,lo(int_main)`
`l.jalr r3`	`l.jalr r3`
`l.nop`	`l.nop`

`l.lwz r2,0x4(r1)`	`l.lwz r3,0x4(r1)`
`l.lwz r4,0x8(r1)`	`l.lwz r4,0x8(r1)`
`l.lwz r5,0xc(r1)`	`l.lwz r5,0xc(r1)`
`l.lwz r6,0x10(r1)`	`l.lwz r6,0x10(r1)`
`l.lwz r7,0x14(r1)`	`l.lwz r7,0x14(r1)`
`l.lwz r8,0x18(r1)`	`l.lwz r8,0x18(r1)`
Line 430...	Line 460...
`l.lwz r27,0x64(r1)`	`l.lwz r27,0x64(r1)`
`l.lwz r28,0x68(r1)`	`l.lwz r28,0x68(r1)`
`l.lwz r29,0x6c(r1)`	`l.lwz r29,0x6c(r1)`
`l.lwz r30,0x70(r1)`	`l.lwz r30,0x70(r1)`
`l.lwz r31,0x74(r1)`	`l.lwz r31,0x74(r1)`
`l.lwz r3,0x78(r1)`

`l.mtspr r0,r0,SPR_PICSR`

	`l.lwz r2, 0x0(r1)`
`l.addi r1,r1,128`	`l.addi r1,r1,128`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`


`_align:`	`_align:`
`l.sw 0x0c(r1),r3`	`l.sw 0x0c(r1),r3`
`l.sw 0x10(r1),r4`	`l.sw 0x10(r1),r4`
`l.sw 0x14(r1),r5`	`l.sw 0x14(r1),r5`
`l.sw 0x18(r1),r6`	`l.sw 0x18(r1),r6`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [reset.S] - Diff between revs 175 and 246