URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [sim.cfg] - Diff between revs 175 and 246

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 175	Rev 246
Line 72...	Line 72...
`pattern to fill memory, used if type = 'pattern'.`	`pattern to fill memory, used if type = 'pattern'.`

`nmemories =`	`nmemories =`
`number of memory instances connected`	`number of memory instances connected`

`instance specific:`
`baseaddr =`	`baseaddr =`
`memory start address`	`memory start address`

`size =`	`size =`
`memory size`	`memory size`
Line 85...	Line 84...
`memory block name`	`memory block name`

`ce =`	`ce =`
`chip enable index of the memory instance`	`chip enable index of the memory instance`

	`mc =`
	`memory controller this memory is connected to`

`delayr =`	`delayr =`
`cycles, required for read access, -1 if instance does not support reading`	`cycles, required for read access, -1 if instance does not support reading`

`delayw =`	`delayw =`
`cycles, required for write access, -1 if instance does not support writing`	`cycles, required for write access, -1 if instance does not support writing`
Line 102...	Line 104...
`/*random_seed = 12345`	`/*random_seed = 12345`
`type = random*/`	`type = random*/`
`pattern = 0x00`	`pattern = 0x00`
`type = unknown /* Fastest */`	`type = unknown /* Fastest */`


`nmemories = 3`
`device 0`
`name = "FLASH"`	`name = "FLASH"`
`ce = 0`	`ce = 0`
	`mc = 0`
`baseaddr = 0xf0000000`	`baseaddr = 0xf0000000`
`size = 0x00800000`	`size = 0x01000000`
`delayr = 10`	`delayr = 1`
`delayw = -1`	`delayw = -1`
`enddevice`	`end`

	`section memory`
	`/*random_seed = 12345`
	`type = random*/`
	`pattern = 0x00`
	`type = unknown /* Fastest */`

`device 1`
`name = "RAM"`	`name = "RAM"`
`ce = 1`	`ce = 1`
	`mc = 0`
`baseaddr = 0x00000000`	`baseaddr = 0x00000000`
`size = 0x00400000`	`size = 0x02000000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 1`
`enddevice`	`end`

	`section memory`
	`/*random_seed = 12345`
	`type = random*/`
	`pattern = 0x00`
	`type = unknown /* Fastest */`

`device 2`
`name = "SRAM"`	`name = "SRAM"`
	`mc = 0`
`ce = 2`	`ce = 2`
`baseaddr = 0x08000000`	`baseaddr = 0xa4000000`
`size = 0x00400000`	`size = 0x00100000`
`delayr = 1`	`delayr = 1`
`delayw = 2`	`delayw = 1`
`enddevice`
`end`	`end`


`/* IMMU SECTION`	`/* IMMU SECTION`

Line 244...	Line 255...
`missdelay =`	`missdelay =`
`number of cycles ic miss costs`	`number of cycles ic miss costs`
`*/`	`*/`

`section ic`	`section ic`
`enabled = 1`	`enabled = 0`
`nsets = 256`	`nsets = 512`
`nways = 1`	`nways = 1`
`blocksize = 16`	`blocksize = 16`
`hitdelay = 0`	`hitdelay = 20`
`missdelay = 0`	`missdelay = 20`
`end`	`end`


`/* DC SECTION`	`/* DC SECTION`

Line 288...	Line 299...
`store_missdelay =`	`store_missdelay =`
`number of cycles dc load miss costs`	`number of cycles dc load miss costs`
`*/`	`*/`

`section dc`	`section dc`
`enabled = 1`	`enabled = 0`
`nsets = 256`	`nsets = 512`
`nways = 1`	`nways = 1`
`blocksize = 16`	`blocksize = 16`
`load_hitdelay = 0`	`load_hitdelay = 20`
`load_missdelay = 0`	`load_missdelay = 20`
`store_hitdelay = 0`	`store_hitdelay = 20`
`store_missdelay = 0`	`store_missdelay = 20`
`end`	`end`


`/* SIM SECTION`	`/* SIM SECTION`

Line 359...	Line 370...

`exe_log_fn = ""`	`exe_log_fn = ""`
`filename for the exection log file.`	`filename for the exection log file.`
`valid only if 'exe_log' is set`	`valid only if 'exe_log' is set`

`spr_log = 0/1`
`'0': log reads/writes to/from sprs`
`'1': don't log reads/write to/from sprs`

`spr_log_fn = ""`
`filename for the sprs log file.`
`valid only if 'spr_log' is set`

`clkcycle = [ps\|ns\|us\|ms]`	`clkcycle = [ps\|ns\|us\|ms]`
`specifies time measurement for one cycle`	`specifies time measurement for one cycle`
`*/`	`*/`

`section sim`	`section sim`
`/* verbose = 1 */`	`verbose = 1`
`debug = 0`	`debug = 0`
`profile = 0`	`profile = 0`
`prof_fn = "sim.profile"`	`history = 0`
	`/exe_log = 1/`
`history = 1`	`/exe_log_fn = "exe.log"/`
`/* iprompt = 0 */`	`clkcycle = 10ns`
`exe_log = 0`
`exe_log_type = software`
`exe_log_start = 0`
`/* exe_log_end = 20000000*/`
`exe_log_marker = 10000`
`exe_log_fn = "executed.log"`

`spr_log = 0`
`spr_log_fn = "spr.log"`
`clkcycle = 100ns`
`end`	`end`


`/* SECTION VAPI`	`/* SECTION VAPI`

Line 439...	Line 432...
`upr =`	`upr =`
`changes the upr register`	`changes the upr register`

`sr =`	`sr =`
`sets the initial Supervision Register value`	`sets the initial Supervision Register value`
	`supervisor mode (SM) and fixed one (FO) set = 0x8001`
	`exception prefix high (EPH, vectors@0xf0000000) = 0x4000`
	`together, (SM \| FO \| EPH) = 0xc001`
`superscalar = 0/1`	`superscalar = 0/1`
`'0': CPU is scalar`	`'0': CPU is scalar`
`'1': CPU is superscalar`	`'1': CPU is superscalar`
`(modify cpu/or32/execute.c to tune superscalar model)`	`(modify cpu/or32/execute.c to tune superscalar model)`

Line 462...	Line 457...
`sbuf_len =`	`sbuf_len =`
`length of store buffer (<= 256), 0 = disabled`	`length of store buffer (<= 256), 0 = disabled`
`*/`	`*/`

`section cpu`	`section cpu`
`ver = 0x1200`	`ver = 0x12`
`rev = 0x0001`	`cfg = 0x00`
	`rev = 0x01`
	`sr = 0x8001 /SPR_SR_FO \| SPR_SR_SM \| SPR_SR_EPH /`
`/* upr = */`	`/* upr = */`
`superscalar = 0`	`superscalar = 0`
`hazards = 0`	`hazards = 0`
`dependstats = 0`	`dependstats = 0`
`sbuf_len = 0`	`sbuf_len = 0`
Line 544...	Line 541...
`valid only if gdb_enabled is set`	`valid only if gdb_enabled is set`

`vapi_id =`	`vapi_id =`
`Used to create "fake" vapi log file containing the JTAG proxy messages.`	`Used to create "fake" vapi log file containing the JTAG proxy messages.`
`*/`	`*/`

`section debug`	`section debug`
`enabled = 0`	`enabled = 0`
`gdb_enabled = 0`	`/* gdb_enabled = 0 */`
`server_port = 9999`	`/* server_port = 9999*/`
	`rsp_enabled = 1`
	`rsp_port = 50001`
`end`	`end`


`/* MC SECTION`	`/* MC SECTION`

Line 565...	Line 563...
`baseaddr =`	`baseaddr =`
`address of first MC register`	`address of first MC register`

`POC =`	`POC =`
`Power On Configuration register`	`Power On Configuration register`

	`index =`
	`Index of this memory controller amongst all the memory controllers`
`*/`	`*/`

`section mc`	`section mc`
`enabled = 0`	`enabled = 0`
`baseaddr = 0x93000000`	`baseaddr = 0x93000000`
`POC = 0x00000008 /* Power on configuration register */`	`POC = 0x00000008 /* Power on configuration register */`
	`index = 0`
`end`	`end`


`/* UART SECTION`	`/* UART SECTION`

Line 635...	Line 637...

`section uart`	`section uart`
`enabled = 1`	`enabled = 1`
`baseaddr = 0x90000000`	`baseaddr = 0x90000000`
`irq = 2`	`irq = 2`
`channel = "file:uart0.rx,uart0.tx"`	`/* channel = "file:uart0.rx,uart0.tx" */`
	`/* channel = "tcp:10084" */`
	`channel = "xterm:"`
`jitter = -1 /* async behaviour */`	`jitter = -1 /* async behaviour */`
`16550 = 1`	`16550 = 1`
`end`	`end`


Line 704...	Line 708...
`vapi_id =`	`vapi_id =`
`VAPI id of this instance`	`VAPI id of this instance`
`*/`	`*/`

`section ethernet`	`section ethernet`
	`enabled = 1`
`baseaddr = 0x92000000`	`baseaddr = 0x92000000`
`dma = 0`	`/* dma = 0 */`
`irq = 4`	`irq = 4`
`rtx_type = 0`	`rtx_type = 0`
`tx_channel = 0`	`/* tx_channel = 0 */`
`rx_channel = 1`	`/* rx_channel = 1 */`
`rxfile = "eth0.rx"`	`rxfile = "eth0.rx"`
`txfile = "eth0.tx"`	`txfile = "eth0.tx"`
`sockif = "eth0"`	`sockif = "eth0"`
`end`	`end`

Line 735...	Line 740...
`first VAPI id of this instance`	`first VAPI id of this instance`
`GPIO uses 8 consecutive VAPI IDs`	`GPIO uses 8 consecutive VAPI IDs`
`*/`	`*/`

`section gpio`	`section gpio`
`enabled = 1`	`enabled = 0`
`baseaddr = 0x91000000`	`baseaddr = 0x91000000`
`irq = 3`	`irq = 3`
`base_vapi_id = 0x0200`	`base_vapi_id = 0x0200`
`end`	`end`

Line 762...	Line 767...
`filename = ""`	`filename = ""`
`template name for generated names (e.g. "primary" produces "primary0023.bmp")`	`template name for generated names (e.g. "primary" produces "primary0023.bmp")`
`*/`	`*/`

`section vga`	`section vga`
`enabled = 1`	`enabled = 0`
`baseaddr = 0x97100000`	`baseaddr = 0x97100000`
`irq = 8`	`irq = 8`
`refresh_rate = 100000`	`refresh_rate = 100000`
`filename = "primary"`	`filename = "primary"`
`end`	`end`
Line 776...	Line 781...

`This section configures tick timer`	`This section configures tick timer`

`enabled = 0/1`	`enabled = 0/1`
`whether tick timer is enabled`	`whether tick timer is enabled`

`irq =`
`irq number`
`*/`	`*/`
`/*`
`section tick`	`section pic`
`enabled = 1`	`enabled = 1`
`irq = 0`	`edge_trigger = 1`
`end`	`end`
`*/`

`/* FB SECTION`	`/* FB SECTION`

`This section configures the frame buffer`	`This section configures the frame buffer`

Line 808...	Line 809...
`filename = ""`	`filename = ""`
`template name for generated names (e.g. "primary" produces "primary0023.bmp")`	`template name for generated names (e.g. "primary" produces "primary0023.bmp")`
`*/`	`*/`

`section fb`	`section fb`
`enabled = 1`	`enabled = 0`
`baseaddr = 0x97000000`	`baseaddr = 0x97000000`
`refresh_rate = 1000000`	`refresh_rate = 1000000`
`filename = "primary"`	`filename = "primary"`
`end`	`end`

Line 827...	Line 828...
`rxfile = ""`	`rxfile = ""`
`filename, where to read data from`	`filename, where to read data from`
`*/`	`*/`

`section kbd`	`section kbd`
`enabled = 1`	`enabled = 0`
`irq = 5`	`irq = 5`
`baseaddr = 0x94000000`	`baseaddr = 0x94000000`
`rxfile = "kbd.rx"`	`rxfile = "kbd.rx"`
`end`	`end`

Line 878...	Line 879...

`FIXME: irq number`	`FIXME: irq number`
`*/`	`*/`

`section ata`	`section ata`
`enabled = 1`	`enabled = 0`
`baseaddr = 0x9e000000`	`baseaddr = 0x9e000000`
`irq = 15`	`irq = 15`

`dev_type0 = 1`
`dev_file0 = "/tmp/sim_atadev0"`
`dev_size0 = 1`
`dev_packet0 = 0`

`dev_type1 = 0`
`dev_file1 = ""`
`dev_size1 = 0`
`dev_packet1 = 0`
`end`	`end`


`/* CUC SECTION`

`This section configures the OpenRISC Custom Unit Compiler`

`memory_order = none/weak/strong/exact`
`none different memory ordering, even if there are dependencies,`
`burst can be made, width can change`
`weak different memory ordering, if there cannot be dependencies`
`burst can be made, width can change`
`strong same memory ordering, burst can be made, width can change`
`exact exacltly the same memory ordering and widths`

`calling_convention = 0/1`
`whether programs follow OpenRISC calling conventions`

`enable_bursts = 0/1`
`whether burst are detected`

`no_multicycle = 0/1`
`if selected no multicycle logic paths will be generated`

`timings_fn = ""`
`*/`

`section cuc`
`memory_order = weak`
`calling_convention = 1`
`enable_bursts = 1`
`no_multicycle = 1`
`timings_fn = "virtex.tim"`
`end`

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [sim.cfg] - Diff between revs 175 and 246