OpenCores

URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [sim.cfg] - Diff between revs 419 and 467

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 419	Rev 467
Line 119...	Line 119...
`/*random_seed = 12345`	`/*random_seed = 12345`
`type = random*/`	`type = random*/`
`/*pattern = 0x00`	`/*pattern = 0x00`
`type = unknown */`	`type = unknown */`

`type = exitnops`	`/type = exitnops/`

`name = "RAM"`	`name = "RAM"`
`ce = 1`	`ce = 1`
`mc = 0`	`mc = 0`
`baseaddr = 0x00000000`	`baseaddr = 0x00000000`
Line 714...	Line 714...
`section ethernet`	`section ethernet`
`enabled = 1`	`enabled = 1`
`baseaddr = 0x92000000`	`baseaddr = 0x92000000`
`/* dma = 0 */`	`/* dma = 0 */`
`irq = 4`	`irq = 4`
`rtx_type = 0`	`rtx_type = "tap"`
`/* tx_channel = 0 */`	`/* tx_channel = 0 */`
`/* rx_channel = 1 */`	`/* rx_channel = 1 */`
`rxfile = "eth0.rx"`	`/* rxfile = "eth0.rx"*/`
`txfile = "eth0.tx"`	`/txfile = "eth0.tx"/`
`sockif = "eth0"`	`/sockif = "eth0"/`
	`phy_addr = 7`
	`tap_dev = "tap0"`


`end`	`end`


`/* GPIO SECTION`	`/* GPIO SECTION`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.